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Posts Tagged ‘SpyGlass’

How to avoid timing exception pitfalls

Tuesday, August 20th, 2013

We often think that we’ve got the timing job nailed down and that there aren’t any problems that we can’t easily, almost routinely solve.  Using timing exceptions to optimize synthesis or P&R shouldn’t be a problem.

However, making an error when specifying timing exceptions can possibly shut down a design project.

Take a look at what Atrenta’s Shaker Sarwary, Ramesh Dewangan and Sridhar Gangadharan say about how to avoid this situation:

http://alturl.com/99bbs

(Note:  white paper download requires registration)

LeePR does work for Atrenta.

 

Who’s getting hit by the double whammy of verification?

Thursday, October 25th, 2012

 

Piyush Sancheti

In a recent article written by EDA industry watcher Ann Steffora Mutschler, Atrenta’s VP of Product Marketing Piyush Sancheti pointed to the curse of the verification double whammy for engineers:

“For verification engineers and for designers, this is a double whammy,” noted Piyush Sancheti, vice president of product marketing at Atrenta. “If you ask a digital design or digital verification team, they will tell you that low-power design and the introduction of analog/mixed-signal components on what used to be a simple digital chip is a significant verification challenge. For verification engineers what this means is your finite state machines or your control logic just got that much more complicated. If you go from 2 domains to 20 domains, your verification complexity just increased an order of magnitude.”

We caught up with Piyush in the Atrenta hallway and asked him to elaborate on his statement.  Here’s what he said:

Ed:   So what is the double whammy and why should we care?

Piyush: With the onset of A/MS and low power requirements, digital design teams now have to contend with two new foreign entries to their previous monolithic design environment.

Ed:  And they are…?

Piyush:  New logic blocks that are completely foreign to digital designers and the implementation of power management techniques like power & voltage domains. Voltage domains allow the timing critical portions of the design at a higher voltage (overdrive), and the rest at a lower voltage (underdrive). Power domains, on the other hand, allow one to turn off the power on entire blocks of the design when not in use.

Ed:  Haven’t digital designers always needed to be conscious and conscientious about power?

Piyush:  Not to the extent they must be these days.    Here’s the challenge – say you are designing a chip for a smart phone.  When you are watching a YouTube video, you don’t need the phone function, so you want to make sure that the phone functions are off.  What’s the result?  You’re saving power, or in consumer terms, preserving battery life.   But, if the smart phone gets a call, you have to be sure the phone function turns on instantly, without adversely impacting your video viewing experience.  So designers have to make sure the domains turn off and on in perfect harmony, almost like conducting a symphony.

So what’s the problem?  New power management logic that designers are not used to has been thrust on them rapidly and recently.  They need to get up to speed fast.  This is not an easy job. Not only that, but you now have very complex finite state machines that switch these functions on and off seamlessly.

Ed:  So what’s the solution?

Piyush:   A comprehensive methodology for functional and structural verification.

Ed:  Can you elaborate?

Piyush:  These complex finite state machines must be verified exhaustively for functional correctness. You need to make sure that the various functions on your smart phone wake up and shut off in a timely manner without adversely impacting the device behavior, and ultimately the user experience. With structural verification you need to make sure that the perimeter of the voltage and power domains are properly secured. When you have signals crossing one voltage domain to another, you need voltage level shifters. Similarly, you need isolation logic between power domains, to ensure that signals don’t float to unknown values when a domain is powered off.

Ed:  So what sort of tools and methodologies do you see out there to meet the double whammy challenge?

Piyush:  Well, of course, I’m most familiar with the Atrenta platform.   There are undoubtedly other ways to go about this job.  But from what I see, SpyGlass Power is being used by many large chip and system companies for static signoff of power and voltage domains. SpyGlass Advanced Lint enables exhaustive finite state machine verification using formal techniques. And with our recent acquisition of NextOp Software, we now have BugScope to ensure dynamic verification (simulation) is covering all the corner cases that are now part of your design because of this increased complexity.

Ed:  So your final words of wisdom?

Piyush:  Verification of modern day SoC designs is a daunting task. But like any complex problem a systematic approach using a combination of static and dynamic verification techniques will help you reach your device ambitions faster.

 

 

 

–        Note:  Lee PR does work for Atrenta.

Renesas on SpyGlass Physical

Monday, August 20th, 2012

 

 

Yasushi Ozaki, Director of Engineering Department overseeing product design and Development, at Renesas, spoke at the Atrenta Technology Forum First inYokohama.  This is Tech-On’s coverage of his presentation and his evaluation of SpyGlass Physical, which is an EDA tool for estimating chip area and logic depth at the RTL stage:

http://www.nikkeibp.co.jp/article/news/20120720/316569/

 

 

 

 

Lee PR does work for Atrenta

 

The SpyGlass® value interviews

Friday, June 1st, 2012

 

 

Atrenta has pulled together quite a slate of customers, partners, an industry observer and EDA’s premier investor to talk about the value SpyGlass brings to each of their realms. It’ll be interesting to hear how this signature product has proliferated in different environments! Atrenta invites you to stop by and hear how SpyGlass improves productivity @ Xilinx, Vivante, Sonics and Arteris and why Dan Nenni and Jim Hogan see SpyGlass as the consummate ubiquitous product in EDA.

The talks will be held at Atrenta’s booth #2230.

Monday, June 4

9:30 am…..Jack Browne, Sonics
10:30 am…Frederic Rivoallon, Xilinx
2:00 pm…..Halim Theny, Vivante

Tuesday, June 5

10:30 am…Charlie Janac, Arteris
2:00 pm…..Frederic Rivoallon, Xilinx
3:00 pm…..Dan Nenni, SemiWiki
5:00 pm…..Jack Browne, Sonics

Wednesday, June 6

10:30 am…Charlie Janac, Arteris
12:30 pm…Jim Hogan

……………………….

 
Note: Lee PR does work for Atrenta

Atrenta’s unified platform

Tuesday, May 15th, 2012

Maybe Atrenta is saying goodbye to the thought-bubble guy…..

Atrenta’s SpyGlass has always been the dominant name in the company’s brand portfolio,and for good reason. It’s the dominant product in RTL design analysis, verification and optimization.

Now, Atrenta is reconfiguring its product lineup to formalize this state of affairs. SpyGlass now becomes the unifying platform for all Atrenta products.  Sort of the mother ship that all Atrenta products are based on.

So what’s a unified platform? All the tools now share a common set up and debugging methodology and tighter GUI. And what can users verify and optimize from this new unified platform? Syntax, power, testability, clock synchronization, timing and routing congestion. All at the RTL stage, well before detailed implementation begins.

(more…)

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