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Posts Tagged ‘SoC’

The RTL signoff conversation goes to Asia

Wednesday, August 28th, 2013

 

Atrenta will discuss what RTL signoff requirements are needed for SoC designers in China, South Korea and Taiwan at their upcoming seminars in September and October.

Click here for more information.

 

 

 

 

 

 

LPR does work for Atrenta

How to avoid timing exception pitfalls

Tuesday, August 20th, 2013

We often think that we’ve got the timing job nailed down and that there aren’t any problems that we can’t easily, almost routinely solve.  Using timing exceptions to optimize synthesis or P&R shouldn’t be a problem.

However, making an error when specifying timing exceptions can possibly shut down a design project.

Take a look at what Atrenta’s Shaker Sarwary, Ramesh Dewangan and Sridhar Gangadharan say about how to avoid this situation:

http://alturl.com/99bbs

(Note:  white paper download requires registration)

LeePR does work for Atrenta.

 

IP up front at DAC

Tuesday, May 14th, 2013

These two trend setters share their opinions on the BIG DAC themes in 2013.

I see two related trends:

1) More signoff activity earlier in the design flow

2) More focus on IP quality and usability

Both of these trends represent a maturing of design tools and business models. Because of the tremendous complexity that sub-20 nm design brings, it becomes more important to get the design right as early as possible. The tools are maturing in the earlier stages, and more designers are demanding clean reports, or sign-off level quality audits as a result.  This is helping to reduce schedule delays and design costs – good for the industry.

Semiconductor IP is also maturing – both use models and business models.  There is a growing focus on reporting delivered quality and robustness.  This will allow IP providers that deliver the best IP to flourish.  Also good for the industry.  We’ll see an increase in conversations about IP providers collaborating with the rest of the ecosystem at DAC.  Another good trend.

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One Final Prediction for 2013 – an opportunity for start-ups?

Monday, February 25th, 2013

 

So you thought our blog last week was our last prediction?  Just kidding.

We actually have one more prophesy……from Michel Courtoy, esteemed EDA executive, entrepreneur and angel investor.

“As a member of the EDA community, when I look at 2013, I see a key dynamic in our customer base: chip = SoC. Across the board now, designs are created by combining multiple IPs from different sources that include embedded processors, multiple interfaces and memories. This is true across the spectrum from simple microcontrollers, to multi-function chips for consumer devices, all the way to the most complex multi-core microprocessors. Hence technologies that accelerate the design and verification of SoCs will thrive while technologies targeting the IP-level will find a saturated market.

Internal to the EDA market, we have been bombarded with messages of gloom triggered by the consolidation that has eliminated most ‘mid-size’ EDA suppliers, leaving mainly the ‘Big 3 and the 100 dwarfs’. Well, this might be the opportunity that the start-ups need: where will the Big 3 fill their shopping cart now when looking for new technologies? To stay competitive, the Big 3 have to go back to acquiring start-ups and find a way to monetize new technologies in their sales channel. This will reinvigorate the ecosystem for EDA start-ups and lead to more innovation.

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Who’s getting hit by the double whammy of verification?

Thursday, October 25th, 2012

 

Piyush Sancheti

In a recent article written by EDA industry watcher Ann Steffora Mutschler, Atrenta’s VP of Product Marketing Piyush Sancheti pointed to the curse of the verification double whammy for engineers:

“For verification engineers and for designers, this is a double whammy,” noted Piyush Sancheti, vice president of product marketing at Atrenta. “If you ask a digital design or digital verification team, they will tell you that low-power design and the introduction of analog/mixed-signal components on what used to be a simple digital chip is a significant verification challenge. For verification engineers what this means is your finite state machines or your control logic just got that much more complicated. If you go from 2 domains to 20 domains, your verification complexity just increased an order of magnitude.”

We caught up with Piyush in the Atrenta hallway and asked him to elaborate on his statement.  Here’s what he said:

Ed:   So what is the double whammy and why should we care?

Piyush: With the onset of A/MS and low power requirements, digital design teams now have to contend with two new foreign entries to their previous monolithic design environment.

Ed:  And they are…?

Piyush:  New logic blocks that are completely foreign to digital designers and the implementation of power management techniques like power & voltage domains. Voltage domains allow the timing critical portions of the design at a higher voltage (overdrive), and the rest at a lower voltage (underdrive). Power domains, on the other hand, allow one to turn off the power on entire blocks of the design when not in use.

Ed:  Haven’t digital designers always needed to be conscious and conscientious about power?

Piyush:  Not to the extent they must be these days.    Here’s the challenge – say you are designing a chip for a smart phone.  When you are watching a YouTube video, you don’t need the phone function, so you want to make sure that the phone functions are off.  What’s the result?  You’re saving power, or in consumer terms, preserving battery life.   But, if the smart phone gets a call, you have to be sure the phone function turns on instantly, without adversely impacting your video viewing experience.  So designers have to make sure the domains turn off and on in perfect harmony, almost like conducting a symphony.

So what’s the problem?  New power management logic that designers are not used to has been thrust on them rapidly and recently.  They need to get up to speed fast.  This is not an easy job. Not only that, but you now have very complex finite state machines that switch these functions on and off seamlessly.

Ed:  So what’s the solution?

Piyush:   A comprehensive methodology for functional and structural verification.

Ed:  Can you elaborate?

Piyush:  These complex finite state machines must be verified exhaustively for functional correctness. You need to make sure that the various functions on your smart phone wake up and shut off in a timely manner without adversely impacting the device behavior, and ultimately the user experience. With structural verification you need to make sure that the perimeter of the voltage and power domains are properly secured. When you have signals crossing one voltage domain to another, you need voltage level shifters. Similarly, you need isolation logic between power domains, to ensure that signals don’t float to unknown values when a domain is powered off.

Ed:  So what sort of tools and methodologies do you see out there to meet the double whammy challenge?

Piyush:  Well, of course, I’m most familiar with the Atrenta platform.   There are undoubtedly other ways to go about this job.  But from what I see, SpyGlass Power is being used by many large chip and system companies for static signoff of power and voltage domains. SpyGlass Advanced Lint enables exhaustive finite state machine verification using formal techniques. And with our recent acquisition of NextOp Software, we now have BugScope to ensure dynamic verification (simulation) is covering all the corner cases that are now part of your design because of this increased complexity.

Ed:  So your final words of wisdom?

Piyush:  Verification of modern day SoC designs is a daunting task. But like any complex problem a systematic approach using a combination of static and dynamic verification techniques will help you reach your device ambitions faster.

 

 

 

–        Note:  Lee PR does work for Atrenta.

On Power Awareness in RTL design analysis: Update to a Brian Bailey-designated Top Ten Atrenta article

Wednesday, October 10th, 2012

 

Narayana Koduri’s article on Power Awareness in RTL Design Analysis was the second of two Atrenta articles that EE Times editor Brian Bailey named as the ten most-read contributed articles published in EDA Designline.    Along with number one article Understanding Clock Domain Issues  by Saurabh Verma and Ashima Dabare, Atrenta appears to be the only company with two articles in this top ten list.

So even though his article appeared in July 2012, we asked Narayana to give us an update on what he sees as the power awareness challenges.  Here’s what he had to say.

Ed:  Narayana,   your article sure addressed a hot topic in SoC design. And judging by the readers you got, the design community liked what you had to say.  What can you add to your July 2012 article?

Narayana:  Thanks Ed.   From what I can see, due to aggressive low power requirements, power domains are being implemented in a growing number of SoC designs to reduce both leakage and dynamic power.

Ed:  How so?

Narayana:  UPF or CPF can be used to define the power intent to capture information such as power domains, level shifter requirements, isolation cells, retention cells, power switch cells, etc. These specifications will help implementation tools and verification tools to deal with the power intent properly.

Ed:  So how best to deal with power intent?

Narayana:   RTL tools that verify aspects of the SoC such as clock domain crossings, testability, timing and routing congestion need to be aware of the power intent. If not, the verification is not complete and this may lead to design failures or a costly re-spin of the design. This need for power-aware verification is driving new requirements in the EDA tool flow.

NOTE:  For an update on Understanding Clock Domain Issues see our blog of October 3.

 

 

 

 

Note:  Lee PR does work for Atrenta

 

Top article on EE Times: authors give an update to CDC challenges

Wednesday, October 3rd, 2012

Ashima Dabare

Saurabh Verma

 

 

 

 

 

 

 

On the heels of EE Times editor Brian Bailey naming their article “Understanding clock domain issues” the number one article on EDA Designline, we checked in with authors Saurabh Verma and Ashima Dabare on what they see as developments and new challenges since they wrote their 2007 article. Here’s what they said.

Ed: It appears that your article got twice the number of views as the number two article. Congratulations on the EE Times recognition!

Obviously, CDC was an important design issue in 2007 and it certainly is today. What would you say to designers today?

Ashima: CDC design is evolving and so are the synchronization techniques and verification tools. Since we have written this article we have witnessed new challenges posed to CDC verification tools.

One that comes to mind is evolving synchronization styles. In addition to clever variations of synchronization techniques introduced by designers trying to meet their design objective or schedule, new architectures such as those required for a network on a chip (NoC) have been introduced which in turn require verification tools to re-invent themselves.

Recently CDC tools have introduced generic synchronization verification techniques that do not rely on the structure of the synchronizer and analyze clock domain crossings at the protocol level allowing them to better recognize synchronizers, reduce “noise” and improve root cause analysis.

Saurabh: Also, global chip design dictates blocks and IPs to be designed in various geographical locations. The person doing CDC verification is rarely the designer. CDC verification tools are now challenged with providing root-cause analysis of CDC problems to people who have little knowledge of the block.

I also see as a fact that design size is fast growing and so are the number of clocks and clock domains. Combined with the move toward global chip development, flat CDC verification of large SoCs would be a painful exercise where bugs can easily slip through.

The divide and conquer approach seems to be the best possible approach. To begin with, the lower level blocks should be analyzed and CDC issues, if any, should be fixed at the block level itself. Once all the individual blocks are CDC clean, their abstract models can be plugged in and the complete design can be analyzed for CDC issues at the interconnect level.

Ed: So how would you sum up what CDC design needs in 2012?

Ashima: With the ever increasing complexity of design styles, robust CDC verification is indispensable to enable successful chips in the first silicon attempt!

 

Note:  as near as we can tell, Atrenta is the only company to place two articles in Bailey’s top ten. Narayana Koduri’s Power awareness in RTL design analysis came in as ninth most read. We’ll catch up with him next week, so stay tuned.

 

 

Note: Lee PR does work for Atrenta

Ajoy Bose and Jim Hogan on the systems customers now defining SoC design

Tuesday, September 4th, 2012

 

Jim Hogan

Ajoy Bose

 

 

 

 

 

 

 

Atrenta CEO Ajoy Bose and EDA visionary and investor Jim Hogan spoke at a recent National Institute of Technology (NIT) meeting on the momentous changes we see in who controls chip design these days. Clearly, systems companies like Apple define – even dictate – what they want from their silicon vendors..and these systems customers certainly want a lot more than they did ten years ago.

Jim tells us why we have to care:

Video Part 1

Video Part 2

Power Point Presentation

Ajoy shows us how to care:

Video Part 1

Video Part 2

Power Point Presentation

 

 

 

 

 

Lee PR does work for Atrenta

Renesas on SpyGlass Physical

Monday, August 20th, 2012

 

 

Yasushi Ozaki, Director of Engineering Department overseeing product design and Development, at Renesas, spoke at the Atrenta Technology Forum First inYokohama.  This is Tech-On’s coverage of his presentation and his evaluation of SpyGlass Physical, which is an EDA tool for estimating chip area and logic depth at the RTL stage:

http://www.nikkeibp.co.jp/article/news/20120720/316569/

 

 

 

 

Lee PR does work for Atrenta

 

The dawn of a new business day for EDA?

Monday, July 30th, 2012

Mike Gianfagna, VP of Corporate Marketing

 

 

 

 

 

With Atrenta’s acquisition of NextOp concluded and the corporate and technology integration going forward, we checked in with Atrenta’s Mike Gianfagna about what this means for the industry.   Dawn of a new business day for EDA?

 

Ed:  It’s been about a month now since Atrenta bought NextOp.   What has to happen now?

Mike:  The fanfare is waning.  The news has been reported and analyzed.  The two company’s web sites are one. And now the real work begins as we integrate NextOp technology with Atrenta technology.

Ed:   So what does all this mean?

Mike:  For Atrenta, it means accelerated growth in the SoC Realization market. We can now address design and verification challenges at RTL and above. For our customers, this will mean improved schedule predictability and lower cost.

Ed:   So now you add functional verification to the RTL platform for SoC design, right?

Mike:   Actually, NextOp’s technology goes beyond functional verification of SoCs.  It also helps with IP qualification and IP reuse – very important focus areas for Atrenta. This technology will improve the completeness and effectiveness of our IP Kit.

Customers will get the previous benefits of early analysis coupled with  functional verification – an area that continues to be very time consuming, expensive and somewhat unpredictable.

Ed:  So what does this mean to the EDA industry?

Mike:   I hope it has a positive impact on the industry as well. EDA has been stagnant for too long. The same customers buying the same tools from the same vendors. It’s time to shake things up a bit.  It’s time for new methodologies, new approaches, new business models and more positive exits for all those hard-working people at private EDA companies.  Can Atrenta’s acquisition of NextOp contribute to this trend in some meaningful way?  I certainly hope so.

 

NOTE:  Lee PR does work for Atrenta.

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