Mike’s dream is for “a vibrant industry with a well-defined quality metric.”
Lee PR does work for Atrenta
What's PR got to do with it?
Posts Tagged ‘semiconductors’
KNTV, the Bay Area NBC affiliate, covered a story this past Friday on how Silicon Valley is the nation’s mecca for startups. KNTV reporter Scott Budman contends that Silicon Valley is stretching its borders north to Oakland. Really?
As part of this story, Budman interviews San Jose EDA firm, Atrenta, pointing to Atrenta as a typical Silicon Valley startup.
Check it out:
With less than 3 weeks away until DAC’13, Liz and I asked Warren Savage about IPextreme’s and Constellations’ planned presence there. Warren is not only founder and CEO of IPextreme, but also head of the IP consortium, Constellations.
We caught up with Warren recently, and Mike Gianfagna, VP of Corporate Marketing at Atrenta (Atrenta is a Constellations partner), happened to be there. So, the two of them let us in on what Constellations would be up to at DAC.
Liz: Warren, what play does IP have at DAC this year?
Warren: Change is slow, but IPextreme and Constellations are happy to report change is afoot and our workshop at DAC serves as a prime example of this. Together with TSMC and our Constellations partners Atrenta and Sonics, we are pleased to present “Driving Quality to the Desktop of the DAC Engineer” on Sunday, June 2 from 1:00 to 5:00 PM. This workshop showcases a foundry, two IP companies, and an EDA company working together—exactly as we do every day.
Why, then, is this the first DAC workshop of its kind? Why have the ties binding us together in the semiconductor ecosystem not been highlighted before? Perhaps the old saying, “If all you have is a hammer, everything looks like a nail,” is the only explanation. At the end of the day, our customers need all of us – both IP providers and EDA vendors. We owe it to them not only to recognize that, but also to make their lives easier by working together.
The final word on the BIG theme(s) for DAC comes from Brian Bailey, Editor of EE Times EDA Designline……
For many people, the attendance numbers seem to be the number one issue on their minds this year. DAC has never been to Austin in its 50 year history and only once been to Texas. Yet there is, and has always been, a very large design community in that area, a group of people that have perhaps been overlooked. A head count seems to be a very unimportant number, even though it is an easy metric. But we are an intelligent industry that should know a lot about metrics and I think there are more useful metrics in this case, such as the number of first time attendees.
DAC is upon us….and in Austin, of all places – the island in the middle of Texas.
As it’s getting closer, we were wondering what the BIG theme is for the 50th DAC. So, we asked a few of our friends and colleagues in the industry. Here’s what a few of them had to say.
I expect DAC to continue to explore low power challenges, with much talk about solving FinFET issues at 14 and 10 nm. Then there is the ever expanding SoC and how to handle all of the challenges that come with greater integration and IP reuse. Finally, what’s DAC without a discussion of Moore’s Law and whether it will/won’t continue to define industry progress in the years to come?
~ Joe Desposito, Editor-in-Chief, Electronic Design
Cary Chin, Director of Technical Marketing at Synopsys, has an intriguing take on how to approach verification now that the mandate for design project managers is to meet the low power requirement of the target end-product. Chin says that if we look at verification in terms of fine and broad “granularity,” users will meet their verification goals with a lot less angst and anguish. However, at first glance, I had no idea what Chin was talking about…which is why we asked him to join us and talk about this idea.
Ed: Cary, you’ve been recently talking about granularity in verification, especially in terms of low power. What does this all mean?
Cary: When I think of granularity in low power design, I’m thinking about the size of the “chunks” that we manipulate to improve the energy efficiency (or “low power performance”) of a design. For example, in most of today’s low power methodologies, large functional blocks are the boundaries we work within – we can shut down these blocks or manipulate the voltage to save energy when peak performance isn’t required. This boundary level isn’t just a matter of convenience; our tools and methodologies for both implementation and verification can only deal with certain levels of complexity, so we are confined in many dimensions in how we can pursue finer granularity.
In a casual conversational exchange I overheard last week at DVCon (which reminded me of what Steve Jobs said to John Scully – “Do you want to sell sugared water for the rest of your life or do you want to…change the world?” – someone asked if the other’s company wanted to dink out press releases forever or if the company wanted to tell a story that mattered to its audiences.
This conversation got me thinking……There’s nothing wrong with sending out press releases but companies get optimal effect and value when they issue press releases for more than mere information distribution.
What would that be? To reinforce, substantiate or bolster the company’s story. Sending out press releases (or saying, writing or doing any outbound efforts) ought to convey at least one of the company’s message points.
Our final prediction for 2013 comes from Mike Gianfagna, VP of Corporate Marketing at Atrenta, and prognosticator extraordinaire:
“By the end of 2013, the names of the Big 3 EDA companies will not be the same as they are today.”
Today’s prediction comes from Ravi Ravikumar, Vice President of Marketing at ICScape Inc. Ravi, who has over 18 years of experience in marketing, business development & project/program management in the EDA and semiconductor industries, gives his two cents on timing and power closure for 2013…..
“If you think timing and power closure were difficult issues at 40 and 28nm, they are going to get worse at 20nm. The traditional means of addressing timing/power closure as a post-implementation step using custom scripts that call on sign-off STA and physical implementation tools to achieve closure is taking too many iterations at 28nm.
As geometries reduce below 28nm, timing/power are more difficult to close due to design-related complex physical requirements, process and manufacturability issues like double/triple patterning and VT cell spacing rules create more R/C effects, impacting timing and power. Power issues in-turn lead to temperature and reliability problems. Design closure becomes a multi-dimensional task.