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Posts Tagged ‘semiconductors’

EDA will auction some really cool stuff

Monday, September 30th, 2013

 

There’s an EDA industry reunion at the Computer History Museum on October 16th. “EDA: Back to the Future” is being put on by EDAC along with several sponsors, and it looks like it will be a night to remember.  To learn more about the event and purchase tickets click here.

Part of this event is a fund raising auction.  I recently talked with Mike Gianfagna at Atrenta about the auction to understand what that part is all about.

 

Ed: Mike, I understand that part of the event on October 16th is a fund raising auction.  Can you tell me a little about that?

Mike:  Sure Ed. The Computer History Museum is working on an exhibit for EDA – one that captures the rich history of this industry and preserves some of its innovation in the form of physical artifacts and some of its pioneers in the form of oral histories, captured on video. It’s a terrific project, but we need money to keep the progress going. The auction on the evening of October 16th is focused on raising that money.

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How to become venturable

Tuesday, September 17th, 2013

 

Are you thinking of starting a hardware company?  Although it takes a lot more for a hardware startup to become “venturable” than a software startup, viable funding can be found.

Ilgiz Akhmetshin, of SKTA Innopartners details several ways for hardware startups to raise additional funds in his blog:  “How to Raise Seed Investments for a Hardware Startup.”

 

 

 

 

Lee PR does work for SKTA Innopartners.

 

The RTL signoff conversation goes to Asia

Wednesday, August 28th, 2013

 

Atrenta will discuss what RTL signoff requirements are needed for SoC designers in China, South Korea and Taiwan at their upcoming seminars in September and October.

Click here for more information.

 

 

 

 

 

 

LPR does work for Atrenta

How to avoid timing exception pitfalls

Tuesday, August 20th, 2013

We often think that we’ve got the timing job nailed down and that there aren’t any problems that we can’t easily, almost routinely solve.  Using timing exceptions to optimize synthesis or P&R shouldn’t be a problem.

However, making an error when specifying timing exceptions can possibly shut down a design project.

Take a look at what Atrenta’s Shaker Sarwary, Ramesh Dewangan and Sridhar Gangadharan say about how to avoid this situation:

http://alturl.com/99bbs

(Note:  white paper download requires registration)

LeePR does work for Atrenta.

 

Webinar on ESL presented by Gary Smith

Tuesday, August 13th, 2013

 

Do you want to know the latest on ESL?  Curious what today’s tools look like?

Gary Smith will be conducting a webinar this coming Monday on this very topic – ESL – are you Ready?

Gary, along with Mike Gianfagna of Atrenta and Jason Andrews and Frank Schirrmeister of Cadence, will examine the evolution of ESL over the past few years and share the breakthroughs that have occurred in the flow.

When is it?

11:00-11:45 am PDT

Monday, August 19, 2013

Gary will be recognizing the industry’s “ESL Heroes.”  Want to know what an ESL Hero is?  Tune in Monday to find out.

You can register for the webinar here.

The Semiconductor Supply Chain Tomorrow

Monday, August 12th, 2013

Before the summer ends and the summer blockbuster movies and DAC become a distant memory (still shaking my head over The Lone Ranger’s flop), let me just share Mike Gianfagna’s vision for next summer’s blockbuster.

It’s a tad more like Terminator 2 than the masked man and Tonto.  And it may not be too far from reality – that’s what’s exciting…..and scary.

Of course it’s about the semiconductor supply chain and how it might affect our lives in the future.

 

Click here to look into the future.

~ Liz

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Reinvigorating semiconductor startup funding

Monday, July 22nd, 2013

For those in fabless semiconductor or IP startup mode (or even thinking about how to start up and get funding),  take a look at Paul McLellan’s  report on a couple of panel sessions at the annual GSA Entrepreneurship Conference, held last Thursday, July 18 at the Computer History Museum.

Of note is that the first session’s panelists brought a variety of funding models to the table – from a traditional VC to Intel Capital to a brand new incubator on the scene – SKTA Innopartners.  In fact, any of you fabless guys really should talk to Angel Orrantia at SKTA.  They are focused on fabless semiconductors and enterprise software.

Below is an excerpt from Paul’s write-up:

GSA Entrepreneurship: Getting Money In and Out

Paul McLellan

by

Paul McLellan

Published on 07-18-2013 11:32 PM

This afternoon and evening I was at GSA’s entrepreneurship conference at the Computer History Museum. The first two panel sessions were essentially on getting money into companies to get them started (or growing them), and getting money out when you have built the business.

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Budding Semiconductor Entrepreneurs….come attend the GSA Entrepreneurship Conference Thursday July 18

Wednesday, July 17th, 2013

 

 

 

 

 

 

SKTA Innopartners is participating in the flagship panel at the annual GSA (Global Semiconductor Alliance) Entrepreneurship Conference tomorrow, July 18, 2013, from 3:30 to 8:30 p.m. at the Computer History Museum in Mountain View, CA.

Angel Orrantia, founding business development director of SKTA Innopartners, will serve as a panelist on the 4:00 p.m. panel, Fueling Success and Innovation, the first of four panels at the event. According to GSA, this panel “will look at existing and alternative semiconductor funding models that are fueling innovation, spurring investment, and mitigating risk.”

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Design Rule Manual Creation a Bottleneck?

Monday, June 24th, 2013

Sage Design Automation, Inc. announced its founding technology last month and created a lot of customer and media buzz at DAC’13 inAustin.  I bet a lot of people were surprised that design rule manual creation and DRC deck implementation were manual, error-prone  tasks – especially as we get into smaller process geometries – and that they can take years to put one together.

In a way, it’s a lot like writing a long paper on a typewriter, or even by hand.  When you make an error, you use White Out (remember that?) or type back over the error with the erasing ribbon.  There’s no way to correlate the paper’s index, spell check, grammar check or check for consistency.

So we accosted Sage-DA president and CEO Coby Zelnik to ask him about this problem, one that many of us assumed just took care of itself!  Here’s what he had to say.

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The Internet of Things

Sunday, June 16th, 2013

 

As Mike Demler predicted back in May, the “Internet of Things” was all the buzz at DAC this year. 

Freescale CEO Gregg Lowe talked about the opportunities and challenges in his keynote.  

Mentor CEO Wally Rhines said in his keynote that the big growth in the semiconductor industry will come with the Internet of Things. 

It was simultaneously discussed at the GSA European Executive Forum in Munich and the Sensors Expo in Chicago

What do you think? 

Is it the next big thing? 

Can EDA step up to the challenge? 

And what does it mean to our future?

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