Posts Tagged ‘semiconductors’
Monday, May 20th, 2013
With less than 3 weeks away until DAC’13, Liz and I asked Warren Savage about IPextreme’s and Constellations’ planned presence there. Warren is not only founder and CEO of IPextreme, but also head of the IP consortium, Constellations.
We caught up with Warren recently, and Mike Gianfagna, VP of Corporate Marketing at Atrenta (Atrenta is a Constellations partner), happened to be there. So, the two of them let us in on what Constellations would be up to at DAC.
Liz: Warren, what play does IP have at DAC this year?
 Warren Savage
President and CEO
IPextreme Warren: Change is slow, but IPextreme and Constellations are happy to report change is afoot and our workshop at DAC serves as a prime example of this. Together with TSMC and our Constellations partners Atrenta and Sonics, we are pleased to present “Driving Quality to the Desktop of the DAC Engineer” on Sunday, June 2 from 1:00 to 5:00 PM. This workshop showcases a foundry, two IP companies, and an EDA company working together—exactly as we do every day.
Why, then, is this the first DAC workshop of its kind? Why have the ties binding us together in the semiconductor ecosystem not been highlighted before? Perhaps the old saying, “If all you have is a hammer, everything looks like a nail,” is the only explanation. At the end of the day, our customers need all of us – both IP providers and EDA vendors. We owe it to them not only to recognize that, but also to make their lives easier by working together.
 Mike Gianfagna
VP of Corporate Marketing
Atrenta Mike G: The *only* way to achieve better predictability for IP reuse is collaboration between the members of the value chain that produce the IP and use it. The technologies that will be showcased at this workshop are interesting and useful. Perhaps more interesting however is the collaboration between a foundry, an IP seller, an IP provider and an EDA supplier to use those technologies.
Warren: More details about the workshop, including a full agenda and list of presenters, are available on the DAC website, under Workshops. To attend, select “Workshop 6” from the drop-down menu upon registering for DAC.
Ed: What else is IPextreme up to at DAC?
Warren: Our other activities at DAC also highlight our efforts to grow and expand the IP ecosystem. We’re pleased to be contributing to Atrenta’s innovative RTL Signoff Theater at Booth #1847, where we will demonstrate the integration that we have done with SpyGlass and our Xena IP management system. Here again, we see EDA and IP coming together to provide a better product to our customers.
You can visit the DAC section of Atrenta’s website for more information on the RTL Signoff Theater and their other activities in Austin.
Liz: I think I heard you were going to be moderating a Pavillion Panel. Is that true?
Warren: I’m excited to be participating in a number of panels and less-formal discussions at DAC surrounding IP. And yes, it is true. On Wednesday, June 5 at 10:30 AM, you can find me at Booth #509 as I moderate the Pavilion Panel “IP Pitfalls: Avoid the Wild Ride.” A strong panel of IP experts from Synopsys, National Instruments, and Open-Silicon promises to bring audience members an entertaining and informative discussion. Again, further details can be found on the DAC website.
Liz: I also hear that you’ll be kicking it up in Austin in the name of IP? Tell us more.
Warren: IPextreme and the members of our Constellations collective are extremely proud to be part of the groundbreaking Stars of IP party. This event is an industry first, bringing together IP companies and industry partners to co-host a great evening in appreciation of our customers. Held at Six Lounge on Tuesday, June 4, Stars of IP will be a night of bluegrass, beer, and BBQ—a celebration of all things semiconductor IP, with a distinctly Texan twist. This type of industry social event has never been done before, and we hope that the party in Austin is the first of many. It would be wonderful to cultivate a new IP industry tradition that is enjoyable for IP providers and consumers alike. Though the party is invitation-only, we have a handful of tickets available to the general public. Interested parties should email party@ip-extreme.com for more details.
Mike G: By Tuesday evening, I think I will have had a good dose of loud music and huge parties. I’m looking forward to a more intimate setting where good conversation and softer music will prevail.
Ed: How is DAC dealing with IP this year?
Warren: Though it has traditionally been an EDA show, there is an IP presence at DAC if you know where to look. It’s time to bring that to the foreground. If DAC has not yet had its midlife crisis, then the time has come to buy the hot sports car, hop behind the wheel, and burn rubber toward a new format and a brighter future. To move forward and thrive, DAC must take immediate and meaningful steps toward cultivating a greater IP presence alongside EDA at the conference, just as we see happening in the industry itself.
Liz: I’m on that road with you, Warren.
Tags: 50DAC, Atrenta, Chip Design, DAC, DAC'13, DAC2013, Design Automation Conference, EDA, Electronic Design Automation, https://www.facebook.com/pages/Lee-Public-Relations/201964499825219?ref=hl, Intellectual property, IP, IPextreme, semiconductors
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Thursday, May 16th, 2013
The final word on the BIG theme(s) for DAC comes from Brian Bailey, Editor of EE Times EDA Designline……
For many people, the attendance numbers seem to be the number one issue on their minds this year. DAC has never been to Austin in its 50 year history and only once been to Texas. Yet there is, and has always been, a very large design community in that area, a group of people that have perhaps been overlooked. A head count seems to be a very unimportant number, even though it is an easy metric. But we are an intelligent industry that should know a lot about metrics and I think there are more useful metrics in this case, such as the number of first time attendees.
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Tags: 50DAC, Austin, DAC, DAC2013, DAC50, Design Automation Conference, EDA, EDA DesignLine, EE Times, Electronic Design Automation, EUV, FinFETs, https://www.facebook.com/pages/Lee-Public-Relations/201964499825219?ref=hl, IP, Lee PR, Lee Public Relations, semiconductors
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Tuesday, May 14th, 2013
DAC is upon us….and in Austin, of all places – the island in the middle of Texas.
As it’s getting closer, we were wondering what the BIG theme is for the 50th DAC. So, we asked a few of our friends and colleagues in the industry. Here’s what a few of them had to say.
I expect DAC to continue to explore low power challenges, with much talk about solving FinFET issues at 14 and 10 nm. Then there is the ever expanding SoC and how to handle all of the challenges that come with greater integration and IP reuse. Finally, what’s DAC without a discussion of Moore’s Law and whether it will/won’t continue to define industry progress in the years to come?
~ Joe Desposito, Editor-in-Chief, Electronic Design
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Tags: Chip Design, DAC, Design Automation Conference, EDA, Electronic Design, Electronic Design Automation, FinFETs, https://www.facebook.com/pages/Lee-Public-Relations/201964499825219?ref=hl, Intellectual property, IP, Lee PR, Microprocessors, semiconductors, The Linley Group
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Monday, April 29th, 2013
We old gen folks bemoan the passing of print, even though we (in truth) haven’t cared about print for a number of years – finding the true value being on the web. I think it’s more symbolic for us old folks than anything else.
In the wake of the closing of the print editions by UBM, we decided to follow up with the new gen EDA folks we interviewed last week to get their take on this turn of events.
First up is Hannah Watanabe, of Synopsys, with her thoughts on the news…..
 Hannah Watanabe
My mind goes back and forth when it comes to the whole print versus digital media. Personally, when it comes to books, I prefer to have the print version. There is something about turning a page and being able to physically see and feel how many pages I have read and how many I have left. When I’m done with the book, I can put it on a shelf with all of the other books that I have read and feel a sense of accomplishment.
However, when it comes to magazines or monthly or quarterly publications, I much prefer to have access to a digital copy. Unlike books, which I tend to read at home with a cup of tea and a blanket, I find myself looking at magazines and other publications when I’m on the go. When I’m on the go (say waiting for a dentist appointment), I only have bits and pieces of time to read, so it is much nicer to have a digital version or a magazine or publication on my phone than the whole printed version shoved in my purse. So, in short, I think that it is a good and positive move on EE Time’s part to go completely digital. With the age of smartphones, tablets and other mobile devices, I’m sure that the electronic version has a much larger audience and reach. Of course, I do feel for those who are losing their jobs due to a complete migration to digital.
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Tags: EDA, EE Times, Electronics Design Automation, https://www.facebook.com/pages/Lee-Public-Relations/201964499825219?ref=hl, Lee Public Relations, media, print media, semiconductors, social media, Synopysys, UBM
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Tuesday, April 2nd, 2013
Cary Chin, Director of Technical Marketing at Synopsys, has an intriguing take on how to approach verification now that the mandate for design project managers is to meet the low power requirement of the target end-product. Chin says that if we look at verification in terms of fine and broad “granularity,” users will meet their verification goals with a lot less angst and anguish. However, at first glance, I had no idea what Chin was talking about…which is why we asked him to join us and talk about this idea.
Ed: Cary, you’ve been recently talking about granularity in verification, especially in terms of low power. What does this all mean?
Cary: When I think of granularity in low power design, I’m thinking about the size of the “chunks” that we manipulate to improve the energy efficiency (or “low power performance”) of a design. For example, in most of today’s low power methodologies, large functional blocks are the boundaries we work within – we can shut down these blocks or manipulate the voltage to save energy when peak performance isn’t required. This boundary level isn’t just a matter of convenience; our tools and methodologies for both implementation and verification can only deal with certain levels of complexity, so we are confined in many dimensions in how we can pursue finer granularity.
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Tags: EDA, Electronic Design Automation, granularity, hardware, low power, low-power verification, Moore's Law, power, RTL, semiconductors, software, Synopsys, UPF, verification
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Monday, March 4th, 2013
 In a casual conversational exchange I overheard last week at DVCon (which reminded me of what Steve Jobs said to John Scully – ”Do you want to sell sugared water for the rest of your life or do you want to…change the world?” – someone asked if the other’s company wanted to dink out press releases forever or if the company wanted to tell a story that mattered to its audiences.
This conversation got me thinking……There’s nothing wrong with sending out press releases but companies get optimal effect and value when they issue press releases for more than mere information distribution.
What would that be? To reinforce, substantiate or bolster the company’s story. Sending out press releases (or saying, writing or doing any outbound efforts) ought to convey at least one of the company’s message points.
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Tags: Apple, Chip Design, EDA, Electronic Design Automation, PR, public relations, Semiconductor IP, semiconductors
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Monday, February 11th, 2013
Today’s prediction comes from Ravi Ravikumar, Vice President of Marketing at ICScape Inc. Ravi, who has over 18 years of experience in marketing, business development & project/program management in the EDA and semiconductor industries, gives his two cents on timing and power closure for 2013…..
“If you think timing and power closure were difficult issues at 40 and 28nm, they are going to get worse at 20nm. The traditional means of addressing timing/power closure as a post-implementation step using custom scripts that call on sign-off STA and physical implementation tools to achieve closure is taking too many iterations at 28nm.
As geometries reduce below 28nm, timing/power are more difficult to close due to design-related complex physical requirements, process and manufacturability issues like double/triple patterning and VT cell spacing rules create more R/C effects, impacting timing and power. Power issues in-turn lead to temperature and reliability problems. Design closure becomes a multi-dimensional task.
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Tags: design closure, EDA, Electronic Design Automation, ICScape, power, semiconductors, Timing
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Monday, February 4th, 2013
Our next prediction comes from respected blogger, consultant and software architect, algorithm, EDA and cloud computing expert, Olivier Coudert.
 Olivier Coudert In 2013, one major semiconductor company will use the services of a third party to offload its computing resource requirements (for synthesis, simulation, signoff, shared project, or anything they deem important) to the cloud. This third party will work with EDA vendors and cloud providers to build virtual design centers, where customers are given the means to develop, test, and sign off their product. And when I say “cloud” I mean major players in the cloud computing market.
Some semiconductor companies have been feeling the pain of capital investment in datacenters they only need at peak hours. So those companies are getting smart and will work with third party companies to access virtual design centers, build on demand, and pay as-they-go.
Soon any startup will have access to the computing resources and the EDA software they need to focus on innovation without breaking the bank. A new model for hardware startups, which the VCs will love. You will no longer need $10M to fund a hardware company, just a few $100Ks.
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Tags: Chip Design, EDA, Electronic Design Automation, semiconductors, The cloud, venture capitol
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Tuesday, January 22nd, 2013
Remember Carnac the Magnificent from The Tonight Show? Well, his son, Warnac the Magnificent, aka Warren Savage, will divine the future of the IP industry this week in our blog. Warren is founder and CEO of IPextreme.
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Tags: Intellectual property, IP, IPextreme, Semiconductor IP, semiconductors
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