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Posts Tagged ‘Semiconductor IP’

Predictions 2012 – Standards and Social Media

Thursday, January 12th, 2012

This year, we’ll see an old standards battle get resolved. Now that all the players are participating in the IEEE Standard 1801 project (IEEE Standard for Design and Verification of Low Power Integrated Circuits), we can finally put the UPF-CPF debate to rest. Let’s hope that peace will reign and the temptation to fight one more time about a single low power standard will be overcome.

Social media will become less of a curiosity or a perceived waste of time for engineers. We’ll see more EDA customers helping answer each other’s questions and sharing more information (nothing proprietary, of course). LinkedIn discussions will have more depth, not simply people posting “read my blog”.

Facebook will remain more of a social vehicle, and for many engineers of our generation, a misunderstood channel. YouTube videos that provide good content – “how-to” and learning opportunities – will become popular. Twitter will remain a mystery for most, while a minority will find it of much value (include me in the minority). Marketers who spam social media channels with marketing-speak will be shunned. And, we’ll have some great guests on Conversation Central radio.

Karen Bartleson
Sr. Director, Community Marketing
Synopsys, Inc.
@karenbartleson
www.synopsys.com/blogs/thestandardsgame
President-Elect, IEEE Standards Association

 

Predictions 2012 – Mergers and 3D

Wednesday, January 11th, 2012

And the predictions begin……

 

With regard to “Events” – 2012 will be a year of further acquisition and consolidation for both the EDA and IP industries.  Some new faces will join the dance, with significant resources at their disposal. It is likely the “Big 3″ will have at least one new name in a year’s time.

With regard to “Breakthroughs” – it’s a different story.  3D stacked-die design still won’t be mainstream in a year’s time.  True hardware/software co-design will still be a developmental area and verification will still be as hard as ever.  Many panels, blogs, seminars and special conference sessions will debate these topics throughout the year with great hope and excitement, however.

Mike Gianfagna
Vice President of Marketing
Atrenta Inc.

http://www.atrenta.com/


 

 

Will it be the end of the world or just shrinking EDA? Mystics Muse about Money, Mergers and Multiple SoCs

Tuesday, January 10th, 2012

 

Step aside Nostradamus and Mayans.  The real earth-shattering events of 2012 could take place in the EDA & IP industries.  We asked industry friends, associates, clients and media folks to ponder what industry-shattering events or breakthroughs we might see in EDA & IP this coming year.

So what topics came up?  Consolidation of the industry; standards; various technologies, 3D being the most discussed; even one man’s blatant personal goal.  :-)

We heard the word “challenge” a lot, for the big vendors and the smaller companies.  So will two foundry-led EDA mega-companies duke it out with a third mega-company, as one diviner foretold?   Tough to tell how tongue-in-cheek his prophesy was.

So we’ll post the visionary comments of one individual at a time, in the order they came into us.  We found them enlightening and even entertaining!  We hope you do too.

 

Liz and Ed

 

Three Shifts for SIP

Tuesday, March 22nd, 2011

Ken Brock is the Product Marketing Manager for DesignWare Logic Libraries at Synopsys.  Ken shared with us here his view of the trends he sees for the future of semiconductor IP.

 

What Does the Future Hold for Semiconductor IP?

The marketplace for semiconductor IP (SIP) continues to grow at double digit rates. According to Gartner Dataquest, the number of third-party semiconductor design IP blocks in an average chip design will double from the current level and the SIP market will reach $2.3B in 2014. IBS and Semico believe the SIP market will be greater than $3 billion in 2014.

We see six major trends in IP:

  • Convergence: The increased demand for “Smart” consumer electronics is driving more features and functionality into a single device such as the latest craze in tablets shown at this year’s Consumer Electronics Show (CES). This trend is causing significant changes in SoC designs in areas such as power and performance requirements that drive technology node migrations, and in increased clock frequencies to keep up with bandwidth needs.
  • Core versus Context: Does this function differentiate the SoC? Interfaces like PCI Express® and USB have to work but they don’t generally differentiate the SoC.  As an IP vendor, we see many different applications spaces for our IP and we have to ensure that IP works over a broad range of configurations and products.
  • Fab-outsourcing: More outsourcing of manufacturing means more opportunity for customers to use off-the-shelf IP to meet their design requirements, and more demand for IP vendors to create high-quality IP on the most advanced process nodes.
  • Power, Performance, Area: As many semiconductor designs compete for the key sockets, having the fastest performance, lowest power and smallest area is often a key differentiator of the design with respect to processor performance, battery life, packaging cost and silicon cost. Choices of foundation IP (memory and logic) providers make a big difference between winners and also-rans.
  • Consumer-driven schedules: Shorter time-to-market and more features means that designers need to de-risk schedules by using high-quality IP solutions that have been proven time and time again in the market place.
  • Expense control: It is often less expensive for companies to buy third-party IP than to develop it themselves. This is particularly true in advanced nodes where the complexity of IP development increases rapidly with increasing data rates, restricted design rules and increasing variability. As an example, our estimate is that a 28nm standard cell and memory IP platform is at least five to 10 times as complex to design and verify as compared to a similar platform at 40nm.

With these trends as the backdrop, we see significant shifts in the SIP market as it continues to evolve during the next five years:

  • Most SoCs will have about 70 to 80 percent of their functionality in reused IP (internal and/or 3rd party). The majority of these IP blocks will be memories with thousands of instances per chip all connected with a variety of standard cell configurations. Optimized standard cells and memories can significantly impact the performance, power and area of a SoC.
  • Individual IP products will yield to more complex IP subsystems. These subsystems will include application-specific blocks and software. IP integration services will become increasingly important to validate the IP in the system context.
  • Multi-core designs will drive increasingly complex architectures. A virtual prototype of the IP and the larger SoC will enable earlier and more efficient development of application software and middleware.

This is a pivotal time for the semiconductor IP industry as companies strive to develop the best solutions to help designers accelerate their time from concept to implementation. These solutions generate value throughout the design chain by accelerating hardware/software integration and systems validation, allowing efficient SoC architecture exploration and optimization, creating and optimizing functional blocks, and using high-quality semiconductor IP. Designers are turning to trusted third-party SIP solutions to help integrate advanced functionality with the least amount of risk. Winners will choose wisely.

 

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