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Posts Tagged ‘Semiconductor IP’

Predictions 2014: Bob Smith on the watchword for the semiconductor industry

Wednesday, February 19th, 2014

Bob Smith, Senior VP Marketing & Business Development at Uniquify, shared with us his predictions for semiconductor IP in 2014.

“If 2014 has a watchword for the Semiconductor Industry, it would be momentum and that would be a result of the rapidly increasing use of IP in SoC designs. Add on the mushrooming need for ‘adaptive’ IP to mitigate timing and variation challenges in complex SoCs as performance issues multiply and process geometries shrink.

Moves within the DDR memory space continue to rock the industry and create momentum. Designers are heading directly to the latest JEDEC standard LPDDR4 (low-power DDR4) and moving beyond (or even skipping) LPDDR3 because they’re getting greater gains in performance and low power, an important consideration for mobile applications.

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Predictions 2014: Mike Demler on the ecosystem triad

Monday, February 17th, 2014

Next up in our series of predictions is the astute insight of Mike Demler, Senior Analyst with The Linley Group & MICROPROCESSOR report, and former EDA & Chip Design news analyst.  

“It’s all about the ecosystem triad: EDA + foundry + IP.  Cadence and Synopsys continue to evolve more in the IP direction, and there is really not much to say about the tools that hasn’t been said for a long time —just make it all work together!  Redundant “standards” and artificial barriers to interoperability cost the semiconductor industry by lowering productivity.  This is the problem with the disaggregated model. Back in the days when “real men” had fabs, companies could develop complete design flows without such obstacles.

The triad needs to work together to get over the stall inMoore’s Law at 28nm.  Foundries are incurring delays in getting to 16/14nm FinFETS, and almost nobody is going to use 20nm. The chip industry needs an overall lower-cost solution in order to make sub-28nm processes economically viable.  Forget 3D ICs, those will be niche products for a long time, about as popular as 3D TV.

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Predictions 2014: Bryon Moyer on what’s needed from IP and EDA

Wednesday, February 12th, 2014

 

Bryon Moyer, Technology Editor at EE Journal, weighs in on what the chip industry needs from EDA and IP in 2014. 

“At the low level, this is going to be the year where the push and pull between EDA companies and users determines how easy FinFETs are to design with.

At the high level, it feels to me like IP and EDA need to come closer together. For years, logic design has been done using text because higher-level languages allow better design abstraction and productivity for hand-crafted designs than prior schematic approaches did. When IP entered the scene, designs were mostly hand-done, with occasional bits farmed out to IP. But now IP dominates, whether internal or third-party. Rather than having a custom-logic paradigm that accommodates IP, it feels like we need to move more to an IP paradigm that accommodates custom logic. And it’s not just about logic either: mixed signal is everywhere, and should be included more seamlessly.”

 

Predictions 2014: Saankhya’s Anindya Saha on what EDA/IP vendors need to do for their users

Thursday, February 6th, 2014

Anindya Saha, Associate VP (VLSI) at Saankhya Labs, shares his insights on what EDA and IP vendors need to do for their users in 2014. 

“Today the EDA and IP companies alike are in the race to cater to the big semiconductor players by offering the greatest IP in the latest process geometries. However, semiconductor startups, – such as Saankhya – do not change process nodes very quickly because it may not necessarily make business sense.  Here is why.

‘Process design margins’ is a fact of life, which we need to add when we use the latest process nodes. Incorporating these design margins simply adds to the overall SoC design cycle time which we want to keep to a minimum. Hence staying with the older process nodes may be a more prudent choice. When we look at the IP domain, we can categorize the available IPs into the following buckets – Analog IPs, Standard Cell and Memory IPs, Processor Soft Cores and Connectivity IPs.  Besides the usual PPA (Power, Performance and Area) metrics, what we look at for each of these categories is the metric of Power Efficiency. This metric can be based on mW/Mhz or in some cases mW/sq. mm depending on the kind of tradeoffs which we intend to do at System level.

The following are some of the issues I feel EDA and IP companies should address, especially in the domain of standard cell and memory IPs which are commonly used in almost all ASIC Designs today.  (more…)

Predictions 2014 – Atrenta’s Robert Beanland on SoC Integration for 2014

Monday, February 3rd, 2014

Robert Beanland, Senior Director, Corporate Marketing at Atrenta, weighed in on what EDA and IP vendors need to do in 2014.  

“Ahhh, the age old question of, ‘What does EDA and IP need to do this year?’  Well, …

The IP folks need a way to provide fully validated IP to their customers with not only a good understanding of all the validation that has been done, but also the expected use model and configurations for the IP. The use model is critical because it is quite common for IP to be ‘abused’ in a way or mode that the IP vendor never expected. When this happens, the customer must be able to assess the problem in-situ and work with the IP vendor to find a resolution. A standardized quality metric is much more desirable than the current option of comparing each vendor’s unique assessment of their validation. This validation and analysis should include, but is not limited to, power, clock domains, testability and physical. The ‘clean’ IP can then be used with more confidence by their customers in their SoC integration.

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Predictions 2014: Simon Bloch of Samsung Electronics on What do EDA and IP vendors need to do in 2014?

Wednesday, January 29th, 2014

Next up in our series is Simon Bloch’s forecast for 2014.  Simon is Sr. Director of Samsung Electronics R&D, in mobile consumer wireless devices.

“The future of electronics is looking bright! Market forecasters predict growth in literally every category of electronic markets ranging from smart mobile and wearable devices, appliances and sensors connected to a network of Internet of Everything to smart connected cars and cities.

In today’s electronics products, sophisticated hardware is becoming insufficient for product success. Many layers of stacked software control the underlying hardware and determine a product’s competitiveness via functionality, performance, power and cost. And while there is always going to be a need to create new semiconductor components and IC companies will need EDA tools, EDA vendors need to expand the view of Electronics and treat software stack as an integrated part of EDA.

There are many opportunities to come up with products in the software stack space around Linux/Android operating systems and in the area of hardware virtualization. Just last month, CyanogenMod, a company that provides Android based software widely used in the mobile industry, secured $23 million in funding from top tier VCs.  CyanogenMod is a software stack product and contains many features not found in Google versions of the operating system.

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Predictions 2014 – eSilicon’s Mike Gianfagna on IP Integration for 2014

Monday, January 27th, 2014

 

We asked Mike Gianfagna, VP of Marketing at eSilicon and former VP of Corporate Marketing at Atrenta, about EDA, IP and the chip industry in 2014. 

Ed:  What does EDA and IP need to do in 2014?

Mike:  Work more effectively with each other. IP integration continues to be a huge bottleneck for SoC design.  A more uniform quality metric and a way to enforce it is desperately needed. This problem can’t be solved in isolation.  EDA and IP companies need to collaborate to tame this issue.  They can do it.

Ed:  What does the chip industry want from EDA and IP in 2014?

Mike:  The same thing really. Every SoC project is dependent on somebody’s IP.  Whether it’s internally supplied or provided by your favorite IP supplier or your favorite ASIC supplier, the requirement for easy integration with no surprises is the same. Better collaboration between members of the SoC supply chain will definitely help.

 

 

 

Predictions 2014: Angel Orrantia, of VC SKTA Innopartners, on the revitalized semiconductor ecosystem.

Sunday, January 19th, 2014

 

Next up in our series of 2014 forecasts we have the sage predictions of Angel Orrantia, Business Development Director at SKTA Innopartners LLC….

 

 

“Aside from some massive players, the rest of the chip industry has been forced to adopt capital light business models.  Simultaneously, we’re seeing the mask costs making advanced nodes prohibitively expensive.

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What’s Silicon Valley without the Silicon?

Monday, November 18th, 2013

 

Angel Orrantia
Business Development Director
SKTA Innopartners LLC

 

SKTA Innopartners director Angel Orrantia spoke with the San Jose Mercury’s Peter Delevett on why Silicon Valley’s VC community has to start investing again in hardware.

Sure, as Orrantia infers, hardware is tougher (and will probably take longer) to get an exit out of.   But hardware is how electronics ultimately works with its human users.   So funding the hardware ecosystem in, say semiconductors, is absolutely crucial to Silicon Valley’s continued role as the mecca for high tech innovation.

That’s why Orrantia says it’s time to put the silicon back in Silicon Valley.

Read the article here.

 

 

 

Lee PR does work for SKTA Innopartners

The RTL signoff conversation goes to Asia

Wednesday, August 28th, 2013

 

Atrenta will discuss what RTL signoff requirements are needed for SoC designers in China, South Korea and Taiwan at their upcoming seminars in September and October.

Click here for more information.

 

 

 

 

 

 

LPR does work for Atrenta

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