Open side-bar Menu
 What's PR got to do with it?

Posts Tagged ‘register transfer level’

What is the IoT?…Jim Hogan convenes discussion at DAC

Tuesday, May 20th, 2014

_MG_7133-no-halo (2)_medium

 

As DAC frenzy hits us all, here’s an event that EDA/IP users and media people ought to consider attending.

 

It’s a Jim Hogan-moderated discussion event on

IoT system design concerns

Jim will 1) introduce the topic; 2) spur, moderate, provoke discussion and 3)  sum up what we’ve learned during this session.  Of course, this group of speakers are pretty opinionated and won’t need much provocation.

(more…)

Real RTL Signoff™ is a Comprehensive Signoff

Monday, March 17th, 2014

RTL Signoff is certainly one of the hot topics in chip design circles lately, and one that is garnering great interest and concern.  I chatted recently with Piyush Sancheti, VP of Marketing at Atrenta, on what it is, why it’s a design imperative, and how it should be done.

Liz:  Piyush, thanks for taking the time out to chat with me today on this vital topic…RTL Signoff.

Piyush:  No problem, Liz

Liz:  So, to start out, what is RTL Signoff?

Piyush:  “RTL Signoff” gained momentum as an established concept in 2013. While the concept is not new, a commonly-accepted definition did not exist in the past, which is now beginning to emerge.  Here’s what I think RTL Signoff is: a comprehensive series of well-defined MUST-pass requirements for your RTL before you commit the design to downstream implementation such as synthesis and physical layout. In addition to this complete set of RTL Signoff requirements, you need tools and methodologies to meet the requirement, along with tangible metrics to measure your pass/fail criteria.

(more…)

The RTL signoff conversation goes to Asia

Wednesday, August 28th, 2013

 

Atrenta will discuss what RTL signoff requirements are needed for SoC designers in China, South Korea and Taiwan at their upcoming seminars in September and October.

Click here for more information.

 

 

 

 

 

 

LPR does work for Atrenta

How to avoid timing exception pitfalls

Tuesday, August 20th, 2013

We often think that we’ve got the timing job nailed down and that there aren’t any problems that we can’t easily, almost routinely solve.  Using timing exceptions to optimize synthesis or P&R shouldn’t be a problem.

However, making an error when specifying timing exceptions can possibly shut down a design project.

Take a look at what Atrenta’s Shaker Sarwary, Ramesh Dewangan and Sridhar Gangadharan say about how to avoid this situation:

http://alturl.com/99bbs

(Note:  white paper download requires registration)

LeePR does work for Atrenta.

 

The Semiconductor Supply Chain Tomorrow

Monday, August 12th, 2013

Before the summer ends and the summer blockbuster movies and DAC become a distant memory (still shaking my head over The Lone Ranger’s flop), let me just share Mike Gianfagna’s vision for next summer’s blockbuster.

It’s a tad more like Terminator 2 than the masked man and Tonto.  And it may not be too far from reality – that’s what’s exciting…..and scary.

Of course it’s about the semiconductor supply chain and how it might affect our lives in the future.

 

Click here to look into the future.

~ Liz

(more…)

On Power Awareness in RTL design analysis: Update to a Brian Bailey-designated Top Ten Atrenta article

Wednesday, October 10th, 2012

 

Narayana Koduri’s article on Power Awareness in RTL Design Analysis was the second of two Atrenta articles that EE Times editor Brian Bailey named as the ten most-read contributed articles published in EDA Designline.    Along with number one article Understanding Clock Domain Issues  by Saurabh Verma and Ashima Dabare, Atrenta appears to be the only company with two articles in this top ten list.

So even though his article appeared in July 2012, we asked Narayana to give us an update on what he sees as the power awareness challenges.  Here’s what he had to say.

Ed:  Narayana,   your article sure addressed a hot topic in SoC design. And judging by the readers you got, the design community liked what you had to say.  What can you add to your July 2012 article?

Narayana:  Thanks Ed.   From what I can see, due to aggressive low power requirements, power domains are being implemented in a growing number of SoC designs to reduce both leakage and dynamic power.

Ed:  How so?

Narayana:  UPF or CPF can be used to define the power intent to capture information such as power domains, level shifter requirements, isolation cells, retention cells, power switch cells, etc. These specifications will help implementation tools and verification tools to deal with the power intent properly.

Ed:  So how best to deal with power intent?

Narayana:   RTL tools that verify aspects of the SoC such as clock domain crossings, testability, timing and routing congestion need to be aware of the power intent. If not, the verification is not complete and this may lead to design failures or a costly re-spin of the design. This need for power-aware verification is driving new requirements in the EDA tool flow.

NOTE:  For an update on Understanding Clock Domain Issues see our blog of October 3.

 

 

 

 

Note:  Lee PR does work for Atrenta

 

Renesas on SpyGlass Physical

Monday, August 20th, 2012

 

 

Yasushi Ozaki, Director of Engineering Department overseeing product design and Development, at Renesas, spoke at the Atrenta Technology Forum First inYokohama.  This is Tech-On’s coverage of his presentation and his evaluation of SpyGlass Physical, which is an EDA tool for estimating chip area and logic depth at the RTL stage:

http://www.nikkeibp.co.jp/article/news/20120720/316569/

 

 

 

 

Lee PR does work for Atrenta

 

The dawn of a new business day for EDA?

Monday, July 30th, 2012

Mike Gianfagna, VP of Corporate Marketing

 

 

 

 

 

With Atrenta’s acquisition of NextOp concluded and the corporate and technology integration going forward, we checked in with Atrenta’s Mike Gianfagna about what this means for the industry.   Dawn of a new business day for EDA?

 

Ed:  It’s been about a month now since Atrenta bought NextOp.   What has to happen now?

Mike:  The fanfare is waning.  The news has been reported and analyzed.  The two company’s web sites are one. And now the real work begins as we integrate NextOp technology with Atrenta technology.

Ed:   So what does all this mean?

Mike:  For Atrenta, it means accelerated growth in the SoC Realization market. We can now address design and verification challenges at RTL and above. For our customers, this will mean improved schedule predictability and lower cost.

Ed:   So now you add functional verification to the RTL platform for SoC design, right?

Mike:   Actually, NextOp’s technology goes beyond functional verification of SoCs.  It also helps with IP qualification and IP reuse – very important focus areas for Atrenta. This technology will improve the completeness and effectiveness of our IP Kit.

Customers will get the previous benefits of early analysis coupled with  functional verification – an area that continues to be very time consuming, expensive and somewhat unpredictable.

Ed:  So what does this mean to the EDA industry?

Mike:   I hope it has a positive impact on the industry as well. EDA has been stagnant for too long. The same customers buying the same tools from the same vendors. It’s time to shake things up a bit.  It’s time for new methodologies, new approaches, new business models and more positive exits for all those hard-working people at private EDA companies.  Can Atrenta’s acquisition of NextOp contribute to this trend in some meaningful way?  I certainly hope so.

 

NOTE:  Lee PR does work for Atrenta.

Atrenta acquires NextOp – Could this be the start of something BIG?

Wednesday, June 20th, 2012

 

Gary Smith’s statement about the Atrenta acquisition of NextOp has been bandied about this morning in the news….“This could be the start of something big, and NextOp was an excellent place to start.”

See today’s news and analysis about Atrenta’s acquisition of assertion synthesis vendor NextOp plus an interview with Atrenta and NextOp execs in the following online publications:

EDA Café Blog: What Would Joe Do?

EDA Express

EE Daily News

EE Times News & Analysis

EE Times: EDA DesignLine

Gabe on EDA

SemiWiki

System-Level Design

Tech Design Forums

 

————–

Lee PR does work for Atrenta

Atrenta buys NextOp

Wednesday, June 20th, 2012

 

 

 

 

Atrenta Accelerates Growth in Front End Design with Acquisition of NextOp Software, Inc.

 SpyGlass design productivity enhancements expanded to functional verification for semiconductor and consumer electronics developers

SAN JOSE, Calif — June 20, 2012 — Atrenta Inc., a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries, today announced  that it has acquired NextOp Software, Inc., a leading provider of assertion synthesis technology. Atrenta’s products focus on improving efficiency and reducing cost for the design of complex semiconductor IP and system-on-chip (SoC) devices while NextOp’s products focus on improving efficiency and reducing cost for the functional verification of IPs and SoCs. The combination of both company’s products creates a more complete SoC Realization platform.

The acquisition of NextOp allows Atrenta to expand its de-facto standard SpyGlass® register transfer level (RTL) platform to include functional verification — an important and costly component of advanced SoC design.  Utilizing patented static and formal analysis techniques, the SpyGlass platform currently provides RTL design efficiency improvements in the areas of linting, clock synchronization, power optimization, testability, timing constraints and physical routing congestion. The SpyGlass platform will now be expanded to include functional verification support using NextOp’s patented dynamic assertion synthesis technology, resulting in verification efficiency improvements for semiconductor and consumer electronics developers.

“The addition of NextOp’s functional verification technology will give our customers a distinct advantage by providing complete coverage of front end design activities,” said Dr. Ajoy Bose, chairman, president and CEO of Atrenta. “Atrenta’s customers have come to rely on SpyGlass to verify a broad range of design intent, but functional verification was a missing part of our platform. NextOp’s assertion synthesis completes this part of our offering – Atrenta customers will now have added confidence that their designs will work as expected while meeting schedule and performance requirements. We are very excited to bring these innovative solutions and the resulting expanded benefits to our large customer base. ”

“Atrenta is one of the largest private EDA companies,” said Dr. Yunshan Zhu, president and CEO of NextOp Software.  “NextOp has pioneered assertion synthesis technology. Our tool is now widely deployed in production at multiple tier 1 customers – many of whom also use SpyGlass. Atrenta’s world-class field operation will further accelerate the mainstream adoption of assertion synthesis.”

“I’ve heard good things about NextOp’s verification technology from some impressive customers – the combination of Atrenta’s RTL design and NextOp’s RTL verification technology will improve the entire SoC Realization process,” said Jim Hogan, EDA industry veteran and private investor. “I’m also glad to see private/private acquisitions like this happening again after such a long dry spell. Atrenta could be leading a trend in renewed growth for the EDA sector.”

“With the acquisition of Magma there has been renewed talk about a roll-up in the middle of the EDA community,” saidGary Smith, founder and chief analyst for Gary SmithEDA.  “The most obvious candidates are the RTL sign-off tool vendors, and the most talked about driver, of the roll-up, has been Atrenta.  This could be the start of something big, and NextOp was an excellent place to start.”

NextOp’s BugScope assertion synthesis tool will be sold and supported by the combined Atrenta/NextOp worldwide field organization. Dr. Yunshan Zhu will assume the role of vice president, new technologies reporting to Dr. Ajoy Bose. Dr. Yuan Lu, co-founder and CTO of NextOp will assume the role of chief verification architect reporting to Dr. Zhu.  Financial terms of the transaction were not disclosed.

About Assertion Synthesis

Assertion synthesis leverages design and test bench information to automatically generate high quality assertions and functional coverage properties.  Generating assertions and coverage properties manually is tedious and error-prone. Assertions represent a machine-readable version of design intent and are used to improve verification completeness. Functional coverage properties identify functional coverage deficiencies providing guidance for verification teams. When used together, design teams can reduce functional verification time and improve overall functional coverage, resulting in lower design costs, better first-time silicon success and improved quality.

About Atrenta

Atrenta’s SpyGlass® Predictive Analysis software platform significantly improves design efficiency for the world’s leading semiconductor and consumer electronics companies. Patented solutions provide early design insight into the demanding performance, power and area requirements of the complex system on chips (SoCs) fueling today’s consumer electronics revolution. More than two hundred companies and thousands of design engineers worldwide rely on SpyGlass to reduce risk and cost before traditional EDA tools are deployed. SpyGlass functions like an interactive guidance system for design engineers and managers, finding the fastest and least expensive path to implementation for complex SoCs.  SpyGlass from Atrenta: Insight. Efficiency. Confidence.   www.atrenta.com

About NextOp Software

NextOp Software, Inc. is focused on delivering assertion-based verification solutions that allow design and verification teams to uncover bugs, expose functional coverage holes, and increase verification observability. NextOp’s BugScope assertion synthesis is the first product to automatically generate whitebox assertions and functional coverage properties in SVA, PSL and Verilog formats. BugScope’s properties are used to drive progressive, targeted verification via robust, executable design specifications for existing simulation, formal and emulation flows. The company is headquartered at2900 Gordon Avenue, Suite 100,Santa Clara,CA95051. For more information, visit www.nextopsoftware.com or call +1 408-830-9885.

*******************************************************

© 2012 Atrenta Inc. All rights reserved. Atrenta, the Atrenta logo and SpyGlass are registered trademarks of Atrenta Inc. BugScope and NextOp are trademarks of NextOp Software, Inc. All others are the property of their respective holders.

This press release contains forward-looking statements. Atrenta disclaims any obligation and does not undertake to update or revise the forward-looking statements in this press release.

 

 

—————————-

Lee PR does work for Atrenta

 

CST Webinar Series



Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
TechJobsCafe - Technical Jobs and Resumes EDACafe - Electronic Design Automation GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy