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Posts Tagged ‘low power’

Granularity and complexity in low power verification

Tuesday, April 2nd, 2013

 

 

Cary Chin, Director of Technical Marketing at Synopsys, has an intriguing take on how to approach verification now that the mandate for design project managers is to meet the low power requirement of the target end-product.   Chin says that if we look at verification in terms of fine and broad “granularity,” users will meet their verification goals with a lot less angst and anguish.    However, at first glance,  I had no idea what Chin was talking about…which is why we asked him to join us and talk about this idea.

 

Ed: Cary,  you’ve been recently talking about granularity in verification, especially in terms of low power.  What does this all mean?  

Cary:  When I think of granularity in low power design, I’m thinking about the size of the “chunks” that we manipulate to improve the energy efficiency (or “low power performance”) of a design.  For example, in most of today’s low power methodologies, large functional blocks are the boundaries we work within – we can shut down these blocks or manipulate the voltage to save energy when peak performance isn’t required.  This boundary level isn’t just a matter of convenience; our tools and methodologies for both implementation and verification can only deal with certain levels of complexity, so we are confined in many dimensions in how we can pursue finer granularity.

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On Power Awareness in RTL design analysis: Update to a Brian Bailey-designated Top Ten Atrenta article

Wednesday, October 10th, 2012

 

Narayana Koduri’s article on Power Awareness in RTL Design Analysis was the second of two Atrenta articles that EE Times editor Brian Bailey named as the ten most-read contributed articles published in EDA Designline.    Along with number one article Understanding Clock Domain Issues  by Saurabh Verma and Ashima Dabare, Atrenta appears to be the only company with two articles in this top ten list.

So even though his article appeared in July 2012, we asked Narayana to give us an update on what he sees as the power awareness challenges.  Here’s what he had to say.

Ed:  Narayana,   your article sure addressed a hot topic in SoC design. And judging by the readers you got, the design community liked what you had to say.  What can you add to your July 2012 article?

Narayana:  Thanks Ed.   From what I can see, due to aggressive low power requirements, power domains are being implemented in a growing number of SoC designs to reduce both leakage and dynamic power.

Ed:  How so?

Narayana:  UPF or CPF can be used to define the power intent to capture information such as power domains, level shifter requirements, isolation cells, retention cells, power switch cells, etc. These specifications will help implementation tools and verification tools to deal with the power intent properly.

Ed:  So how best to deal with power intent?

Narayana:   RTL tools that verify aspects of the SoC such as clock domain crossings, testability, timing and routing congestion need to be aware of the power intent. If not, the verification is not complete and this may lead to design failures or a costly re-spin of the design. This need for power-aware verification is driving new requirements in the EDA tool flow.

NOTE:  For an update on Understanding Clock Domain Issues see our blog of October 3.

 

 

 

 

Note:  Lee PR does work for Atrenta

 

Predictions 2012 – Persistence of Memory

Thursday, February 9th, 2012

To finish off our series of predictions, I would like to point you to another series of interesting and informative prophesies.  Click on the following topics to see these predictions collected by Brian Bailey, Editor of EDA DesignLine.

Industry Trends

Tools

ESL

IP and Physical Design

The Bold Prediction for EDA

 

A big THANK YOU from Ed & me (Liz) to all who shared their eye opening predictions with us.  Click on their names to see their predictions.  Mike Gianfagna, Karen Bartleson, Paul McLellan, Jens Andersen, Bob Smith, Steve Schulz, Mathias Silvant, Herb Reiter, Max Maxfield, Chris Edwards, John Barr.

 

Only time will tell……

 

The Persistence of Memory, 1931, Salvador Dali

 

Predictions 2012 – Double Patterning in Litho

Monday, January 30th, 2012

The main technical breakthroughs we can expect this year will probably revolve around double patterning in lithography as EDA companies try to optimize the technique for density and performance. And it will probably have knock-on effects way up in the design flow, forcing designers to adopt much more regular designs. But, unless EUV sees a major breakthrough, double and further levels of multiple patterning is something people will need to get used to.

Regularity is likely to become a feature of low-power design as well. Although it hurts effective density, the drive to cut power consumption will see much more use made of on-chip redundancy – we’ve already seen some of that in the nVidia Tegra 3 and the ARM Big.Little initiative. We could see those techniques begin to extend into ultralow power circuits using near or subthreshold devices as engineers discover how to model circuits effectively and recover lost performance at very low voltages.  Some of these techniques will also help reinvigorate older processes – using better EDA to trim power consumption instead of relying primarily on process changes to deliver better energy efficiency.

Chris Edwards
Technology writer: Engineering & TechnologyNew ElectronicsLow-Power Design BlogTech Design Forums

 

Predictions 2012 – Power Optimization at EDA Forefront, Radiation Tolerance at 28nm

Wednesday, January 25th, 2012

On the ASIC/SoC side of the fence: Reducing power consumption is becoming increasingly important — I anticipate that this is the year that power will finally come to the forefront of EDA tools — I know that they optimize for power now, but largely as a second thought — like synthesis, for example, optimizes first for area and timing and then for power – I think we’ll see a move to optimize for power as a primary consideration.

On the FPGA side of the fence: As we move to the 28nm node and below, radiation is increasingly of concern with regard to electronic devices. It’s no longer just of interest for aerospace applications — at these low device geometries, radiation can affect chips in terrestrial applications. FPGAs are particularly susceptible because in addition to their normal logic and registers and memory cells they also have configuration cells. In the past, the only radiation-tolerant FPGAs were antifuse based — but these are only one-time-programmable (OTP) and trail the leading edge technology node by one or two generations. SRAM-based FPGAs offer many advantages in terms of reconfigurability and being at the leading edge of technology, but they are more susceptible to radiation events in their configuration cells. My prediction is that we will see more and more efforts from FPGA chip vendors and EDA tool vendors with regard to creating radiation-tolerant designs.

On the personal side of the fence: I predict that people will come to realize that what the world needs is a book about creating radiation-tolerant electronic designs that can be read and understood by folks who DO NOT have a PhD in nuclear physics – a book that is of interest to the people who design silicon chips (both analog and digital), the people who create EDA tools, the companies who manufacture the chips, and even software engineers (have you heard of “radiation tolerant software”?). I further predict that someone will finally realize that I am the best person to write this book and will approach me with a really great sponsorship deal that will bring tears of delight to my eyes :-)

Clive “Max” Maxfield
Maxfield High-Tech Consulting
Editor, Programmable Logic DesignLine, EE Times
www.CliveMaxfield.com

 

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