Posts Tagged ‘Lee Public Relations’
Thursday, February 6th, 2014
Anindya Saha, Associate VP (VLSI) at Saankhya Labs, shares his insights on what EDA and IP vendors need to do for their users in 2014.
“Today the EDA and IP companies alike are in the race to cater to the big semiconductor players by offering the greatest IP in the latest process geometries. However, semiconductor startups, – such as Saankhya – do not change process nodes very quickly because it may not necessarily make business sense. Here is why.
‘Process design margins’ is a fact of life, which we need to add when we use the latest process nodes. Incorporating these design margins simply adds to the overall SoC design cycle time which we want to keep to a minimum. Hence staying with the older process nodes may be a more prudent choice. When we look at the IP domain, we can categorize the available IPs into the following buckets – Analog IPs, Standard Cell and Memory IPs, Processor Soft Cores and Connectivity IPs. Besides the usual PPA (Power, Performance and Area) metrics, what we look at for each of these categories is the metric of Power Efficiency. This metric can be based on mW/Mhz or in some cases mW/sq. mm depending on the kind of tradeoffs which we intend to do at System level.
The following are some of the issues I feel EDA and IP companies should address, especially in the domain of standard cell and memory IPs which are commonly used in almost all ASIC Designs today. (more…)
Monday, February 3rd, 2014
Robert Beanland, Senior Director, Corporate Marketing at Atrenta, weighed in on what EDA and IP vendors need to do in 2014.
“Ahhh, the age old question of, ‘What does EDA and IP need to do this year?’ Well, …
The IP folks need a way to provide fully validated IP to their customers with not only a good understanding of all the validation that has been done, but also the expected use model and configurations for the IP. The use model is critical because it is quite common for IP to be ‘abused’ in a way or mode that the IP vendor never expected. When this happens, the customer must be able to assess the problem in-situ and work with the IP vendor to find a resolution. A standardized quality metric is much more desirable than the current option of comparing each vendor’s unique assessment of their validation. This validation and analysis should include, but is not limited to, power, clock domains, testability and physical. The ‘clean’ IP can then be used with more confidence by their customers in their SoC integration.
Wednesday, January 29th, 2014
Next up in our series is Simon Bloch’s forecast for 2014. Simon is Sr. Director of Samsung Electronics R&D, in mobile consumer wireless devices.
“The future of electronics is looking bright! Market forecasters predict growth in literally every category of electronic markets ranging from smart mobile and wearable devices, appliances and sensors connected to a network of Internet of Everything to smart connected cars and cities.
In today’s electronics products, sophisticated hardware is becoming insufficient for product success. Many layers of stacked software control the underlying hardware and determine a product’s competitiveness via functionality, performance, power and cost. And while there is always going to be a need to create new semiconductor components and IC companies will need EDA tools, EDA vendors need to expand the view of Electronics and treat software stack as an integrated part of EDA.
There are many opportunities to come up with products in the software stack space around Linux/Android operating systems and in the area of hardware virtualization. Just last month, CyanogenMod, a company that provides Android based software widely used in the mobile industry, secured $23 million in funding from top tier VCs. CyanogenMod is a software stack product and contains many features not found in Google versions of the operating system.
Monday, January 27th, 2014
We asked Mike Gianfagna, VP of Marketing at eSilicon and former VP of Corporate Marketing at Atrenta, about EDA, IP and the chip industry in 2014.
Ed: What does EDA and IP need to do in 2014?
Mike: Work more effectively with each other. IP integration continues to be a huge bottleneck for SoC design. A more uniform quality metric and a way to enforce it is desperately needed. This problem can’t be solved in isolation. EDA and IP companies need to collaborate to tame this issue. They can do it.
Ed: What does the chip industry want from EDA and IP in 2014?
Mike: The same thing really. Every SoC project is dependent on somebody’s IP. Whether it’s internally supplied or provided by your favorite IP supplier or your favorite ASIC supplier, the requirement for easy integration with no surprises is the same. Better collaboration between members of the SoC supply chain will definitely help.
Sunday, January 19th, 2014
Next up in our series of 2014 forecasts we have the sage predictions of Angel Orrantia, Business Development Director at SKTA Innopartners LLC….
“Aside from some massive players, the rest of the chip industry has been forced to adopt capital light business models. Simultaneously, we’re seeing the mask costs making advanced nodes prohibitively expensive.
Monday, November 18th, 2013
Business Development Director
SKTA Innopartners LLC
SKTA Innopartners director Angel Orrantia spoke with the San Jose Mercury’s Peter Delevett on why Silicon Valley’s VC community has to start investing again in hardware.
Sure, as Orrantia infers, hardware is tougher (and will probably take longer) to get an exit out of. But hardware is how electronics ultimately works with its human users. So funding the hardware ecosystem in, say semiconductors, is absolutely crucial to Silicon Valley’s continued role as the mecca for high tech innovation.
That’s why Orrantia says it’s time to put the silicon back in Silicon Valley.
Read the article here.
Lee PR does work for SKTA Innopartners
Tuesday, September 17th, 2013
Are you thinking of starting a hardware company? Although it takes a lot more for a hardware startup to become “venturable” than a software startup, viable funding can be found.
Ilgiz Akhmetshin, of SKTA Innopartners details several ways for hardware startups to raise additional funds in his blog: “How to Raise Seed Investments for a Hardware Startup.”
Lee PR does work for SKTA Innopartners.
Wednesday, August 28th, 2013
Atrenta will discuss what RTL signoff requirements are needed for SoC designers in China, South Korea and Taiwan at their upcoming seminars in September and October.
Click here for more information.
LPR does work for Atrenta
Tuesday, August 20th, 2013
We often think that we’ve got the timing job nailed down and that there aren’t any problems that we can’t easily, almost routinely solve. Using timing exceptions to optimize synthesis or P&R shouldn’t be a problem.
However, making an error when specifying timing exceptions can possibly shut down a design project.
Take a look at what Atrenta’s Shaker Sarwary, Ramesh Dewangan and Sridhar Gangadharan say about how to avoid this situation:
(Note: white paper download requires registration)
LeePR does work for Atrenta.