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Posts Tagged ‘IP’

The IoT and Time to Market

Tuesday, July 22nd, 2014

In today’s snippet from the IoT panel, Randy Smith, VP of Marketing at Sonics, gives his views on how the IoT will affect the EDA and IP industries.



Smith:  Time to Market will be more important. The need for software-hardware co-design and speed will equal new applications and solutions for EDA.

A lot of it will be in consumer, which is why there is a lot of hype, because when we think consumer, we think high volumes, perhaps a trillion devices out there.  But what’s different in that market as compared to some other markets is that time to market is so much more critical.

So for IoT, you’re going to need the equivalent of agile software development and hardware.  You’re going to need to respin that design in three months.  It would not be a tremendous surprise if you see some previous ASIC practices like gate arrays start to get more traction again.


The Internet of Everything – What are we really facing?

Monday, July 21st, 2014


As we had previously announced, venture capitalist Jim Hogan moderated a panel at DAC regarding the IoT. 

_MG_7133-no-halo (2)_mediumIt was an eye opener about all things IoT……or maybe we should call it the IoE (The Internet of Everything), or as one prominent editor noted, the IoW (The Internet of Whatever).  Our panelists included:  Gary Smith, Market Analyst, GSEDA; Frank Schirrmeister, Group Director, System Development Suite, Cadence; Bernard Murphy, CTO, Atrenta; and Randy Smith, VP of Marketing, Sonics.

Very lively discussion among panelists, but also from the floor!  Most notably editor Gabe Moretti of Chip Design and Simon Bloch of Samsung.  Bloch, Sr. Director of R&D in mobile consumer wireless devices, posed questions and stimulated discussion to the point where he might be called the unannounced 6th panelist.

Over the next few blogposts, we’ll share snippets of that discussion.  Gary Smith will start us off…..


Real RTL Signoff™ is a Comprehensive Signoff

Monday, March 17th, 2014

RTL Signoff is certainly one of the hot topics in chip design circles lately, and one that is garnering great interest and concern.  I chatted recently with Piyush Sancheti, VP of Marketing at Atrenta, on what it is, why it’s a design imperative, and how it should be done.

Liz:  Piyush, thanks for taking the time out to chat with me today on this vital topic…RTL Signoff.

Piyush:  No problem, Liz

Liz:  So, to start out, what is RTL Signoff?

Piyush:  “RTL Signoff” gained momentum as an established concept in 2013. While the concept is not new, a commonly-accepted definition did not exist in the past, which is now beginning to emerge.  Here’s what I think RTL Signoff is: a comprehensive series of well-defined MUST-pass requirements for your RTL before you commit the design to downstream implementation such as synthesis and physical layout. In addition to this complete set of RTL Signoff requirements, you need tools and methodologies to meet the requirement, along with tangible metrics to measure your pass/fail criteria.


HOW will EDA/IP get beyond the horizon?

Sunday, March 16th, 2014

Brian Fuller -­ editor in chief of the now-lamented EE Times during its best years ­- and I were talking about it being great that there are these predictions about where EDA/IP is going in 2014. Chris Rowen’s wrap up prediction talked about EDA’s need to move beyond component – level focus. Chris isn’t alone in this idea.

The question is:  HOW will EDA/IP get beyond the component level and start looking at what’s beyond the 25-year EDA horizon and how EDA can and must add value.

Brian and I would love to hear what readers out there think…..

Does EDA & IP need to go beyond?

Where does it need to go?

And how will it get there?

Predictions 2014: Chris Rowen talks EDA and IP….and Beyond

Monday, March 3rd, 2014

For our final entry to this series, let me just reiterate our original question…..

What do EDA and IP (as an industry) need to do in 2014 to serve its user base better?

Chris Rowen, Cadence Fellow and Tensilica Founder, will wrap it up with his word on the subject.

“What does the EDA and IP industry need to do in 2014? Simply put, we need to move past EDA.

Let me explain. As an industry, we’re not just about ‘how’ you design something; we’re increasingly about ‘what’ you design.

This comes amid the relentless march of design complexity. It also comes as companies reconsider their position in the electronics ecosystem to try to deliver more value for customers.

For instance, semiconductor vendors are considering where they best fit into the design spectrum and they’re also looking farther upstream to understand market requirements of their customers’ customers. IP providers, for their part, are looking upstream to understand marketing technology requirements better and re-engineering their business models.


Predictions for 2014: Warren Savage on the IoT era

Monday, February 24th, 2014


Next up in our series of predictions Warren Savage, President and CEO of IPextreme, shares with us what he sees in his crystal ball for 2014.  

“As the door closes on a successful 2013 for most companies in the semiconductor industry, the outlook for 2014 is bright as we see an explosion of new devices in the so-called “Internet of Things” era.  Google’s recent $3.2B acquisition of Nest is indicative that this market will soon eclipse the smart phone/tablet era (aka the post-PC era).  The IoT era will bring with it a range of new opportunities for semiconductor companies to exploit that are not mega-devices, but small, specialized technologies that enable opportunities in adjacent markets, like software and data analysis. There may be at least one semiconductor company that exploits this secondary and/or tertiary source of revenue. (more…)

Predictions 2014: Bob Smith on the watchword for the semiconductor industry

Wednesday, February 19th, 2014

Bob Smith, Senior VP Marketing & Business Development at Uniquify, shared with us his predictions for semiconductor IP in 2014.

“If 2014 has a watchword for the Semiconductor Industry, it would be momentum and that would be a result of the rapidly increasing use of IP in SoC designs. Add on the mushrooming need for ‘adaptive’ IP to mitigate timing and variation challenges in complex SoCs as performance issues multiply and process geometries shrink.

Moves within the DDR memory space continue to rock the industry and create momentum. Designers are heading directly to the latest JEDEC standard LPDDR4 (low-power DDR4) and moving beyond (or even skipping) LPDDR3 because they’re getting greater gains in performance and low power, an important consideration for mobile applications.


Predictions 2014: Bryon Moyer on what’s needed from IP and EDA

Wednesday, February 12th, 2014


Bryon Moyer, Technology Editor at EE Journal, weighs in on what the chip industry needs from EDA and IP in 2014. 

“At the low level, this is going to be the year where the push and pull between EDA companies and users determines how easy FinFETs are to design with.

At the high level, it feels to me like IP and EDA need to come closer together. For years, logic design has been done using text because higher-level languages allow better design abstraction and productivity for hand-crafted designs than prior schematic approaches did. When IP entered the scene, designs were mostly hand-done, with occasional bits farmed out to IP. But now IP dominates, whether internal or third-party. Rather than having a custom-logic paradigm that accommodates IP, it feels like we need to move more to an IP paradigm that accommodates custom logic. And it’s not just about logic either: mixed signal is everywhere, and should be included more seamlessly.”


Predictions 2014: Saankhya’s Anindya Saha on what EDA/IP vendors need to do for their users

Thursday, February 6th, 2014

Anindya Saha, Associate VP (VLSI) at Saankhya Labs, shares his insights on what EDA and IP vendors need to do for their users in 2014. 

“Today the EDA and IP companies alike are in the race to cater to the big semiconductor players by offering the greatest IP in the latest process geometries. However, semiconductor startups, – such as Saankhya – do not change process nodes very quickly because it may not necessarily make business sense.  Here is why.

‘Process design margins’ is a fact of life, which we need to add when we use the latest process nodes. Incorporating these design margins simply adds to the overall SoC design cycle time which we want to keep to a minimum. Hence staying with the older process nodes may be a more prudent choice. When we look at the IP domain, we can categorize the available IPs into the following buckets – Analog IPs, Standard Cell and Memory IPs, Processor Soft Cores and Connectivity IPs.  Besides the usual PPA (Power, Performance and Area) metrics, what we look at for each of these categories is the metric of Power Efficiency. This metric can be based on mW/Mhz or in some cases mW/sq. mm depending on the kind of tradeoffs which we intend to do at System level.

The following are some of the issues I feel EDA and IP companies should address, especially in the domain of standard cell and memory IPs which are commonly used in almost all ASIC Designs today.  (more…)

Predictions 2014 – Atrenta’s Robert Beanland on SoC Integration for 2014

Monday, February 3rd, 2014

Robert Beanland, Senior Director, Corporate Marketing at Atrenta, weighed in on what EDA and IP vendors need to do in 2014.  

“Ahhh, the age old question of, ‘What does EDA and IP need to do this year?’  Well, …

The IP folks need a way to provide fully validated IP to their customers with not only a good understanding of all the validation that has been done, but also the expected use model and configurations for the IP. The use model is critical because it is quite common for IP to be ‘abused’ in a way or mode that the IP vendor never expected. When this happens, the customer must be able to assess the problem in-situ and work with the IP vendor to find a resolution. A standardized quality metric is much more desirable than the current option of comparing each vendor’s unique assessment of their validation. This validation and analysis should include, but is not limited to, power, clock domains, testability and physical. The ‘clean’ IP can then be used with more confidence by their customers in their SoC integration.


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