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Posts Tagged ‘GSA’

Reinvigorating semiconductor startup funding

Monday, July 22nd, 2013

For those in fabless semiconductor or IP startup mode (or even thinking about how to start up and get funding),  take a look at Paul McLellan’s  report on a couple of panel sessions at the annual GSA Entrepreneurship Conference, held last Thursday, July 18 at the Computer History Museum.

Of note is that the first session’s panelists brought a variety of funding models to the table – from a traditional VC to Intel Capital to a brand new incubator on the scene – SKTA Innopartners.  In fact, any of you fabless guys really should talk to Angel Orrantia at SKTA.  They are focused on fabless semiconductors and enterprise software.

Below is an excerpt from Paul’s write-up:

GSA Entrepreneurship: Getting Money In and Out

Paul McLellan

by

Paul McLellan

Published on 07-18-2013 11:32 PM

This afternoon and evening I was at GSA’s entrepreneurship conference at the Computer History Museum. The first two panel sessions were essentially on getting money into companies to get them started (or growing them), and getting money out when you have built the business.

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Budding Semiconductor Entrepreneurs….come attend the GSA Entrepreneurship Conference Thursday July 18

Wednesday, July 17th, 2013

 

 

 

 

 

 

SKTA Innopartners is participating in the flagship panel at the annual GSA (Global Semiconductor Alliance) Entrepreneurship Conference tomorrow, July 18, 2013, from 3:30 to 8:30 p.m. at the Computer History Museum in Mountain View, CA.

Angel Orrantia, founding business development director of SKTA Innopartners, will serve as a panelist on the 4:00 p.m. panel, Fueling Success and Innovation, the first of four panels at the event. According to GSA, this panel “will look at existing and alternative semiconductor funding models that are fueling innovation, spurring investment, and mitigating risk.”

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The Internet of Things

Sunday, June 16th, 2013

 

As Mike Demler predicted back in May, the “Internet of Things” was all the buzz at DAC this year. 

Freescale CEO Gregg Lowe talked about the opportunities and challenges in his keynote.  

Mentor CEO Wally Rhines said in his keynote that the big growth in the semiconductor industry will come with the Internet of Things. 

It was simultaneously discussed at the GSA European Executive Forum in Munich and the Sensors Expo in Chicago

What do you think? 

Is it the next big thing? 

Can EDA step up to the challenge? 

And what does it mean to our future?

Stale IP – what do we do about it?

Monday, November 12th, 2012

 

Stale IP is beginning to rear its ugly head.  It’s like having too many books on your bookshelf – always an issue in my house.  Where do you put the new ones?  Which ones do you keep?  What do you do with the ones you don’t want to keep?

I (Liz Massingill) recently polled some experts in the industry to get their stance on stale IP.  Over the next few weeks I’ll share their views with you.

I’ll start with Harrison Beasley, Manager of the Technical Working Groups at Global Semiconductor Alliance (GSA).  Here’s what he had to say:

 

Liz: Stale IP – what is it?

Harrison: IP becomes stale when the underlying code is out of date.  This could be due to changes in a specification, errors found in use, soft IP not being updated, etc.  My assumption is that stale IP will not perform the task for which it was created.

Liz: What’s so bad about it?

Harrison:  Using stale IP could lead to non-functional silicon, tape out delays, end product failures, etc.

Liz: How do we prevent it from being stale?

Harrison: For internal IP, code checks before layout, during timing analysis, during verification, and before final tape-out help ensure the latest IP version is used.  For third party IP, similar rules apply, but the user must coordinate with the IP Supplier to ensure changes are promulgated to the user.

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Riko Radojcic on 3D standards

Monday, April 11th, 2011

Liz and I sat down with Riko Radojcic of Qualcomm to hear his thoughts on how upcoming 3D design and manufacturing would affect the EDA world.    Naturally, the conversation morphed into a discussion about standards that will be required to make 3D adoption pervasive.

Liz: Thanks for taking the time out of your busy schedule to sit down with us, Riko. So let me ask you, what is the relevance or importance of standards in adopting 3D?

Riko: Well, first, let me make a general statement about standards.  Sometimes some of the EDA companies view proprietary formats as a source of competitive advantage – a way of locking in a customer base.  This is especially true when a given company has taken a lead with a given solution, and they fear that opening up a proprietary format would shrink their slice of the market pie. However, in general, design standards, or standard exchange formats, or standard models, tend to make the whole pie bigger, as opposed to affecting the size of any one’s slice of the pie. So, in the long run, standards are good for users, like Qualcomm, and for vendors, like the EDA companies.  I keep referring back to the industry experience with SPICE models and the transition from the proprietary ‘Level 28’ model to the open standard BSim generation of models.  I think with all the brilliance of hindsight, the industry has benefited from an open standard model.

For 3D technology specifically, we are promoting the concept of standards, in order to accelerate the adoption of 3D design and manufacturing methods.  We want to help to line up the supply chain behind the 3D technology. I would say that most people – users, industry observers, EDA vendors, etc. all perceive 3D technology as a disruptive change.  The fear of that change is part of the barrier to adoption.  Standards are the other side of this coin of fear.  They bring down the feeling of fear.

Ed: Is 3D more a barrier to standards?  Are we sabotaging our own efforts?

Riko: There is a lot of FUD in 3D.  It is important to realize that there is 3D and then there is 3D.  Some future 3D implementations – like stacking logic on logic – does require disruptive change in design tools.  We will need design methodologies and tools that comprehend entirely a new dimension of parameters for this class of designs, and until these are developed, standards may even be a bit of a barrier.

On the other hand, 3D in the short term means heterogeneous stacking, like memory on top of logic.  So right now, 3D is not that disruptive.   We only need some minor upgrades to design logic in a smart way, to make stacking DRAM on top of it easier and lower risk. For this class of designs, standards would be extremely helpful – having a standard exchange format so that we have relevant information about die A when designing die B or vice versa would be excellent.  For example designing power distribution network on die A needs to know about power demands on die B.

To accelerate and facilitate adoption, we need more design information.   JEDEC for example is doing a nice job of working on the standards for memories

Liz: What is JEDEC doing?

JEDEC is defining the pin assignment and the pin array configuration required for Wide IO DRAM memories to be stacked on logic die.

Ed: What of vendors’ fears that buying into this format will be giving away too much of their own design data?

Riko: We can all make an investment in a standard format that can provide the right characteristics without exposing too much information.  The emphasis is on format, rather than specific content – which should be proprietary.  Again I like to refer back to SPICE and BSim models – where the model format, units, etc. are standardized, but the specific coefficients in the model are proprietary information of whoever owns the process technology.

Liz: Why is this not happening now?

Riko: We are all driven by financial motives.  No one feels they will make enough money out of it right now – and this is especially true for standards, which, by definition, belong to everybody. However, there could be certain advantages for someone creating a standard and then giving it away.  If you make the rules, you have a better chance of winning the game.

The thing that is required is a series of standard ‘exchange formats’ that would communicate the necessary information about the design of the various die to be stacked,  such that 3D stacking of these die is a low risk enterprise.  Basically to communicate design attributes such as power demand characteristics, thermal and mechanical stress sensitivities, maybe some floorplanning restrictions, etc..

Most of the standards bodies don’t have the capability to develop such standards. They have mechanisms to review a proposed standard and to manage and distribute it afterwards – but not to do the engineering required to develop one.  So, there’s a lack of champions willing to put in the work to develop and promote a standard.  It could be an EDA company, like Apache, or it could be an institution, like IMEC, or it could be an academic entity.

There are some activities going on, though. IMEC is working with Atrenta to develop a PathFinding tool – which may also involve developing a PathFinding exchange format.  Apache has taken the lead in pushing a standard power exchange format for 3D. Perhaps some of the academics could be engaged to develop standard exchange format proposals?  Si2 is willing to take a role in managing the standards, but someone needs to give them something to standardize.  GSA is active and willing to coordinate the discussions. But someone needs to make a proposal so the industry can say “I like it” or “I don’t like it” or whatever.

Liz: So you are looking for another EDA guy to come up to the plate, and then what if someone like Cadence comes up with a competing idea?  Then what?

Riko: Once a product is developed, all the EDA companies are invested in one format or another.  We want to get these standards in front of the product development curve, so that it would be easier for any one company to adopt and comply with a standard, rather than  making up their own format.  This is where the users – such as Qualcomm – come in.  We have the responsibility to demand this.

Ed: So it sounds like so far, we have a lot of discussion, but to a certain extent, some organizations are waiting for others to discuss or define a proposed set of 3D standards.   Other organizations are waiting for that proposal to get adopted before implementing the 3D standards.   How do we get off this merry-go-round?

Riko: I would say, let’s take a stab at partitioning the effort.  Qualcomm proposed this last September, at a SEMI/Sematech sponsored meeting in Taiwan.   We proposed dividing the world into two buckets…one set of players and activities focused on design related standards,  and another for manufacturing related standards. For each bucket of standard related activities, we proposed a suitable existing standards body, a suitable forum for discussion, and a suitable set of champions who would propose appropriate standards.  In the manufacturing domain, it would make sense to use SEMI to manage the standards, and Sematech to provide the Proposals. In the design domain it would make sense to use Si2 to manage the standards, and EDA or academics that are involved with EDA to provide the proposals. That way there would be less overlap and hopefully fewer gaps

Liz: What would happen then?

Riko: In addition, we proposed to create a forum which would be conducive to exploring and kicking around some of the proposed standards.  Standards bodies, by definition have a formal review and balloting mechanism – which tends to be slow.  So, in order to accelerate the discussion a separate forum would be nice.  The Sematech 3D Enablement Center is doing this already for manufacturing-oriented standards.  Let’s work with GSA to create a forum to discuss design-oriented standards, and if (or when) a given proposal is flushed out, give it to Si2 to create a true standard.

Liz: Your 2011 hope or wish for 3D standards?

Riko: That our industry can actually define a standard without having to fight a turf war.   We can do this if we get ahead of the 3D product curve.  But only if we all pitch in.. .

Riko Radojcic, who has over 25 years in the semiconductor industry, is a Director of Engineering at Qualcomm, currently leading the Design-for-Through Silicon Stacking Initiatives.

 

 

 

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