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Posts Tagged ‘FinFETs’

Predictions 2014: Mike Demler on the ecosystem triad

Monday, February 17th, 2014

Next up in our series of predictions is the astute insight of Mike Demler, Senior Analyst with The Linley Group & MICROPROCESSOR report, and former EDA & Chip Design news analyst.  

“It’s all about the ecosystem triad: EDA + foundry + IP.  Cadence and Synopsys continue to evolve more in the IP direction, and there is really not much to say about the tools that hasn’t been said for a long time —just make it all work together!  Redundant “standards” and artificial barriers to interoperability cost the semiconductor industry by lowering productivity.  This is the problem with the disaggregated model. Back in the days when “real men” had fabs, companies could develop complete design flows without such obstacles.

The triad needs to work together to get over the stall inMoore’s Law at 28nm.  Foundries are incurring delays in getting to 16/14nm FinFETS, and almost nobody is going to use 20nm. The chip industry needs an overall lower-cost solution in order to make sub-28nm processes economically viable.  Forget 3D ICs, those will be niche products for a long time, about as popular as 3D TV.


Predictions 2014: Bryon Moyer on what’s needed from IP and EDA

Wednesday, February 12th, 2014


Bryon Moyer, Technology Editor at EE Journal, weighs in on what the chip industry needs from EDA and IP in 2014. 

“At the low level, this is going to be the year where the push and pull between EDA companies and users determines how easy FinFETs are to design with.

At the high level, it feels to me like IP and EDA need to come closer together. For years, logic design has been done using text because higher-level languages allow better design abstraction and productivity for hand-crafted designs than prior schematic approaches did. When IP entered the scene, designs were mostly hand-done, with occasional bits farmed out to IP. But now IP dominates, whether internal or third-party. Rather than having a custom-logic paradigm that accommodates IP, it feels like we need to move more to an IP paradigm that accommodates custom logic. And it’s not just about logic either: mixed signal is everywhere, and should be included more seamlessly.”


The Last Word on DAC Themes

Thursday, May 16th, 2013

The final word on the BIG theme(s) for DAC comes from Brian Bailey, Editor of EE Times EDA Designline……


For many people, the attendance numbers seem to be the number one issue on their minds this year. DAC has never been to Austin in its 50 year history and only once been to Texas. Yet there is, and has always been, a very large design community in that area, a group of people that have perhaps been overlooked. A head count seems to be a very unimportant number, even though it is an easy metric. But we are an intelligent industry that should know a lot about metrics and I think there are more useful metrics in this case, such as the number of first time attendees.


What’s the BIG theme for DAC50?

Tuesday, May 14th, 2013

DAC is upon us….and in Austin, of all places – the island in the middle of Texas.

As it’s getting closer, we were wondering what the BIG theme is for the 50th DAC.  So, we asked a few of our friends and colleagues in the industry.  Here’s what a few of them had to say.


I expect DAC to continue to explore low power challenges, with much talk about solving FinFET issues at 14 and 10 nm. Then there is the ever expanding SoC and how to handle all of the challenges that come with greater integration and IP reuse. Finally, what’s DAC without a discussion of Moore’s Law and whether it will/won’t continue to define industry progress in the years to come?

~ Joe Desposito, Editor-in-Chief, Electronic Design



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