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Posts Tagged ‘Electronic Design Automation’

How to avoid timing exception pitfalls

Tuesday, August 20th, 2013

We often think that we’ve got the timing job nailed down and that there aren’t any problems that we can’t easily, almost routinely solve.  Using timing exceptions to optimize synthesis or P&R shouldn’t be a problem.

However, making an error when specifying timing exceptions can possibly shut down a design project.

Take a look at what Atrenta’s Shaker Sarwary, Ramesh Dewangan and Sridhar Gangadharan say about how to avoid this situation:

http://alturl.com/99bbs

(Note:  white paper download requires registration)

LeePR does work for Atrenta.

 

Webinar on ESL presented by Gary Smith

Tuesday, August 13th, 2013

 

Do you want to know the latest on ESL?  Curious what today’s tools look like?

Gary Smith will be conducting a webinar this coming Monday on this very topic – ESL – are you Ready?

Gary, along with Mike Gianfagna of Atrenta and Jason Andrews and Frank Schirrmeister of Cadence, will examine the evolution of ESL over the past few years and share the breakthroughs that have occurred in the flow.

When is it?

11:00-11:45 am PDT

Monday, August 19, 2013

Gary will be recognizing the industry’s “ESL Heroes.”  Want to know what an ESL Hero is?  Tune in Monday to find out.

You can register for the webinar here.

The Semiconductor Supply Chain Tomorrow

Monday, August 12th, 2013

Before the summer ends and the summer blockbuster movies and DAC become a distant memory (still shaking my head over The Lone Ranger’s flop), let me just share Mike Gianfagna’s vision for next summer’s blockbuster.

It’s a tad more like Terminator 2 than the masked man and Tonto.  And it may not be too far from reality – that’s what’s exciting…..and scary.

Of course it’s about the semiconductor supply chain and how it might affect our lives in the future.

 

Click here to look into the future.

~ Liz

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Kickin’ it up in Austin with Ajoy and Wally

Friday, June 28th, 2013

For some Friday fun….

For those of you who were unable to attend the big 50th DAC party, or you just missed the intro to Asleep at the Wheel, you might find this little video entertaining.

It’s a video of Cowboy Ajoy and Ranger Rhines (aka Ajoy Bose, CEO of Atrenta and Wally Rhines, CEO of Mentor), cutting it up on the Austin City Limits stage to kick off Kickin’ it up in Austin.

Design Rule Manual Creation a Bottleneck?

Monday, June 24th, 2013

Sage Design Automation, Inc. announced its founding technology last month and created a lot of customer and media buzz at DAC’13 inAustin.  I bet a lot of people were surprised that design rule manual creation and DRC deck implementation were manual, error-prone  tasks – especially as we get into smaller process geometries – and that they can take years to put one together.

In a way, it’s a lot like writing a long paper on a typewriter, or even by hand.  When you make an error, you use White Out (remember that?) or type back over the error with the erasing ribbon.  There’s no way to correlate the paper’s index, spell check, grammar check or check for consistency.

So we accosted Sage-DA president and CEO Coby Zelnik to ask him about this problem, one that many of us assumed just took care of itself!  Here’s what he had to say.

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The Internet of Things

Sunday, June 16th, 2013

 

As Mike Demler predicted back in May, the “Internet of Things” was all the buzz at DAC this year. 

Freescale CEO Gregg Lowe talked about the opportunities and challenges in his keynote.  

Mentor CEO Wally Rhines said in his keynote that the big growth in the semiconductor industry will come with the Internet of Things. 

It was simultaneously discussed at the GSA European Executive Forum in Munich and the Sensors Expo in Chicago

What do you think? 

Is it the next big thing? 

Can EDA step up to the challenge? 

And what does it mean to our future?

KNTV talks to EDA firm re startups in Silicon Valley

Monday, May 27th, 2013

KNTV, the Bay Area NBC affiliate, covered a story this past Friday on how Silicon Valley is the nation’s mecca for startups.  KNTV reporter Scott Budman contends that Silicon Valley is stretching its borders north to Oakland.  Really?

According to a survey conducted by the National Venture Capital Association, San Francisco is the nation’s hottest city for tech startups, with San Jose coming in second. Oakland is ranked at No. 11.

As part of this story, Budman interviews San Jose EDA firm, Atrenta, pointing to Atrenta as a typical Silicon Valley startup.

Check it out:

 

http://www.nbcbayarea.com/news/local/Oakland-a-Hot-Tech-Startup-Hub-208709051.html

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IP exerting its presence at DAC

Monday, May 20th, 2013

 

With less than 3 weeks away until DAC’13, Liz and I asked Warren Savage about  IPextreme’s  and Constellations’ planned presence there.  Warren is not only founder and CEO of IPextreme, but also head of the IP consortium, Constellations.

We caught up with Warren recently, and Mike Gianfagna, VP of Corporate Marketing at Atrenta (Atrenta is a Constellations partner), happened to be there.  So, the two of them let us in on what Constellations would be up to at DAC.

 

Liz: Warren, what play does IP have at DAC this year?

Warren Savage
President and CEO
IPextreme

Warren: Change is slow, but IPextreme and Constellations are happy to report change is afoot and our workshop at DAC serves as a prime example of this. Together with TSMC and our Constellations partners Atrenta and Sonics, we are pleased to present “Driving Quality to the Desktop of the DAC Engineer” on Sunday, June 2 from 1:00 to 5:00 PM. This workshop showcases a foundry, two IP companies, and an EDA company working together—exactly as we do every day.

Why, then, is this the first DAC workshop of its kind? Why have the ties binding us together in the semiconductor ecosystem not been highlighted before? Perhaps the old saying, “If all you have is a hammer, everything looks like a nail,” is the only explanation. At the end of the day, our customers need all of us – both IP providers and EDA vendors. We owe it to them not only to recognize that, but also to make their lives easier by working together.

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The Last Word on DAC Themes

Thursday, May 16th, 2013

The final word on the BIG theme(s) for DAC comes from Brian Bailey, Editor of EE Times EDA Designline……

 

For many people, the attendance numbers seem to be the number one issue on their minds this year. DAC has never been to Austin in its 50 year history and only once been to Texas. Yet there is, and has always been, a very large design community in that area, a group of people that have perhaps been overlooked. A head count seems to be a very unimportant number, even though it is an easy metric. But we are an intelligent industry that should know a lot about metrics and I think there are more useful metrics in this case, such as the number of first time attendees.

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IP up front at DAC

Tuesday, May 14th, 2013

These two trend setters share their opinions on the BIG DAC themes in 2013.

I see two related trends:

1) More signoff activity earlier in the design flow

2) More focus on IP quality and usability

Both of these trends represent a maturing of design tools and business models. Because of the tremendous complexity that sub-20 nm design brings, it becomes more important to get the design right as early as possible. The tools are maturing in the earlier stages, and more designers are demanding clean reports, or sign-off level quality audits as a result.  This is helping to reduce schedule delays and design costs – good for the industry.

Semiconductor IP is also maturing – both use models and business models.  There is a growing focus on reporting delivered quality and robustness.  This will allow IP providers that deliver the best IP to flourish.  Also good for the industry.  We’ll see an increase in conversations about IP providers collaborating with the rest of the ecosystem at DAC.  Another good trend.

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DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: IoTPLL



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