What's PR got to do with it?

Posts Tagged ‘Electronic Design Automation’

IP exerting its presence at DAC

Monday, May 20th, 2013

 

With less than 3 weeks away until DAC’13, Liz and I asked Warren Savage about  IPextreme’s  and Constellations’ planned presence there.  Warren is not only founder and CEO of IPextreme, but also head of the IP consortium, Constellations.

We caught up with Warren recently, and Mike Gianfagna, VP of Corporate Marketing at Atrenta (Atrenta is a Constellations partner), happened to be there.  So, the two of them let us in on what Constellations would be up to at DAC.

 

Liz: Warren, what play does IP have at DAC this year?

Warren Savage
President and CEO
IPextreme

Warren: Change is slow, but IPextreme and Constellations are happy to report change is afoot and our workshop at DAC serves as a prime example of this. Together with TSMC and our Constellations partners Atrenta and Sonics, we are pleased to present “Driving Quality to the Desktop of the DAC Engineer” on Sunday, June 2 from 1:00 to 5:00 PM. This workshop showcases a foundry, two IP companies, and an EDA company working together—exactly as we do every day.

Why, then, is this the first DAC workshop of its kind? Why have the ties binding us together in the semiconductor ecosystem not been highlighted before? Perhaps the old saying, “If all you have is a hammer, everything looks like a nail,” is the only explanation. At the end of the day, our customers need all of us – both IP providers and EDA vendors. We owe it to them not only to recognize that, but also to make their lives easier by working together.

Mike Gianfagna
VP of Corporate Marketing
Atrenta

Mike G: The *only* way to achieve better predictability for IP reuse is collaboration between the members of the value chain that produce the IP and use it. The technologies that will be showcased at this workshop are interesting and useful. Perhaps more interesting however is the collaboration between a foundry, an IP seller, an IP provider and an EDA supplier to use those technologies.

Warren: More details about the workshop, including a full agenda and list of presenters, are available on the DAC website, under Workshops. To attend, select “Workshop 6” from the drop-down menu upon registering for DAC.

Ed: What else is IPextreme up to at DAC?

Warren: Our other activities at DAC also highlight our efforts to grow and expand the IP ecosystem. We’re pleased to be contributing to Atrenta’s innovative RTL Signoff Theater at Booth #1847, where we will demonstrate the integration that we have done with SpyGlass and our Xena IP management system. Here again, we see EDA and IP coming together to provide a better product to our customers.

You can visit the DAC section of Atrenta’s website for more information on the RTL Signoff Theater and their other activities in Austin.

Liz: I think I heard you were going to be moderating a Pavillion Panel. Is that true?

Warren: I’m excited to be participating in a number of panels and less-formal discussions at DAC surrounding IP. And yes, it is true. On Wednesday, June 5 at 10:30 AM, you can find me at Booth #509 as I moderate the Pavilion Panel “IP Pitfalls: Avoid the Wild Ride.” A strong panel of IP experts from Synopsys, National Instruments, and Open-Silicon promises to bring audience members an entertaining and informative discussion. Again, further details can be found on the DAC website.

Liz: I also hear that you’ll be kicking it up in Austin in the name of IP? Tell us more.

Warren: IPextreme and the members of our Constellations collective are extremely proud to be part of the groundbreaking Stars of IP party. This event is an industry first, bringing together IP companies and industry partners to co-host a great evening in appreciation of our customers. Held at Six Lounge on Tuesday, June 4, Stars of IP will be a night of bluegrass, beer, and BBQ—a celebration of all things semiconductor IP, with a distinctly Texan twist. This type of industry social event has never been done before, and we hope that the party in Austin is the first of many. It would be wonderful to cultivate a new IP industry tradition that is enjoyable for IP providers and consumers alike. Though the party is invitation-only, we have a handful of tickets available to the general public. Interested parties should email party@ip-extreme.com for more details.

Mike G: By Tuesday evening, I think I will have had a good dose of loud music and huge parties. I’m looking forward to a more intimate setting where good conversation and softer music will prevail.

Ed: How is DAC dealing with IP this year?

Warren: Though it has traditionally been an EDA show, there is an IP presence at DAC if you know where to look. It’s time to bring that to the foreground. If DAC has not yet had its midlife crisis, then the time has come to buy the hot sports car, hop behind the wheel, and burn rubber toward a new format and a brighter future. To move forward and thrive, DAC must take immediate and meaningful steps toward cultivating a greater IP presence alongside EDA at the conference, just as we see happening in the industry itself.

Liz: I’m on that road with you, Warren.

The Last Word on DAC Themes

Thursday, May 16th, 2013

The final word on the BIG theme(s) for DAC comes from Brian Bailey, Editor of EE Times EDA Designline……

 

For many people, the attendance numbers seem to be the number one issue on their minds this year. DAC has never been to Austin in its 50 year history and only once been to Texas. Yet there is, and has always been, a very large design community in that area, a group of people that have perhaps been overlooked. A head count seems to be a very unimportant number, even though it is an easy metric. But we are an intelligent industry that should know a lot about metrics and I think there are more useful metrics in this case, such as the number of first time attendees.

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IP up front at DAC

Tuesday, May 14th, 2013

These two trend setters share their opinions on the BIG DAC themes in 2013.

I see two related trends:

1) More signoff activity earlier in the design flow

2) More focus on IP quality and usability

Both of these trends represent a maturing of design tools and business models. Because of the tremendous complexity that sub-20 nm design brings, it becomes more important to get the design right as early as possible. The tools are maturing in the earlier stages, and more designers are demanding clean reports, or sign-off level quality audits as a result.  This is helping to reduce schedule delays and design costs – good for the industry.

Semiconductor IP is also maturing – both use models and business models.  There is a growing focus on reporting delivered quality and robustness.  This will allow IP providers that deliver the best IP to flourish.  Also good for the industry.  We’ll see an increase in conversations about IP providers collaborating with the rest of the ecosystem at DAC.  Another good trend.

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What’s the BIG theme for DAC50?

Tuesday, May 14th, 2013

DAC is upon us….and in Austin, of all places – the island in the middle of Texas.

As it’s getting closer, we were wondering what the BIG theme is for the 50th DAC.  So, we asked a few of our friends and colleagues in the industry.  Here’s what a few of them had to say.

 

I expect DAC to continue to explore low power challenges, with much talk about solving FinFET issues at 14 and 10 nm. Then there is the ever expanding SoC and how to handle all of the challenges that come with greater integration and IP reuse. Finally, what’s DAC without a discussion of Moore’s Law and whether it will/won’t continue to define industry progress in the years to come?

~ Joe Desposito, Editor-in-Chief, Electronic Design

 

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More new gen thoughts on the passing of print

Tuesday, April 30th, 2013

Today we will hear from McKenzie Mortensen, of IPextreme, on print vs. digital.

McKenzie Mortensen

McKenzie Mortensen

I’m far more on the fence about this topic than I ever thought I would be. In all honesty, I’m not completely sure where I stand. I’ll try to replicate my thought process below:

Pro Print

  • I’m a literature nerd in a very big way—BA English (Writing, Rhetoric, and Culture), MA Children’s Literature, life-long bookworm. I love books—the look, the feel, the smell, the different typefaces, the weight of a volume as I’m reading… it’s a sensory experience as much as it is an intellectual one. I have actually begun collecting antique hardcovers and rare picture books over the past couple of years. From hand bound antiques to glossy coffee table volumes, books are a form of art. 
  • I suffer from a mild obsession with stationery and paper products in general, plus I am an avid paper-crafter. I love to scrapbook and make collages, and magazines often come in very handy for harvesting images. I love cutting up magazines and turning them into something new. I’ve done some really neat things with old book pages also (only from damaged volumes, of course—I could never kill a book without it being a humane death). 
  • There are certain circumstances when I would not feel comfortable having a tablet with me. For example, when I’m going to the beach or hanging out by the pool, the last thing I want to take with me is my iPad. A cheap paperback or a magazine seems a better choice in a wet, sandy environment where damage is likely. 
  • I have a lot of bookworm friends, and one of our favorite things to do is trade books. Until it’s possible to lend a book to a friend digitally, I will need print copies of my favorites so that I can share them with people I know will appreciate them. 
  • Books come from bookstores and libraries, and if I could live in either one, I totally would. The atmosphere is simultaneously calming and invigorating to me, a heady blend of paper, ink, and curiosity. 

 Pro Digital

  • I thought I would always be firmly a print girl, but I run into problems when I travel; as a fairly quick reader, I usually need to take more than one book with me on a trip in order to ensure that I’ll have sufficient reading material. As you can imagine, my carryon bags have been rather weighty at times. I started using my iPad only for travel to avoid the 50-pound hand luggage problem. 
  • The illuminated screen is great for reading under any light conditions without disturbing those around me (on a dark airplane, for instance).
  • I can download another book whenever I want to (well, provided I have Wi-Fi access). Simple!
  • I love that I can highlight passages and make notes easily as I read. You can take the girl out of literary academia, but you can’t take literary academia out of the girl, I guess! I developed a “study as you read” method during my education that I still apply to leisure reading. Such a nerd! Another bonus in this area is that I can easily explore allusions made in the text. I can look up dates and brush up on historical events, for example, as necessary. I can do all of these things when reading a print volume, but it’s not very practical when I’m on the go. 
  • Reading magazines digitally affords me the huge benefit of “clickability.” If an article mentions a restaurant I’d like to try, I can instantly view their website and check out the menu. I can order products or seek more information without having to dog-ear a page and remember to look things up later. 
  • I can bookmark things and save images with ease, and in a very compact amount of space. Like many crafty people, I suffer from a Pinterest addiction.

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New blood making its mark on EDA

Monday, April 15th, 2013

McKenzie Mortensen

Darcy
Pierce

Hannah Watanabe

For more than several years now, Peggy Aycinena has noted the dearth of new blood entering the EDA and IP industry ranks. Those of us who started in the industry in the 1980s still seem to dominate the corporate, engineering and marketing ranks. One area where we do see an infusion of new generation folks is in the marketing communications area. So Liz Massingill and I asked three of the new generation people to allow us to put them on the spot and talk a little about what new and old generation EDA and IP people bring to the party. With us are: McKenzie Mortensen of IPextreme, Darcy Pierce of Synopsys and Hannah Watanabe of Synopsys.

Ed: McKenzie, Darcy, Hannah, thanks for taking the time to speak with us today. So let’s kick off with a question about you. What does the new generation bring to EDA and IP that the old generation doesn’t?

McKenzie: We love to shake things up.

Darcy: One of the more obvious attributes that I think our generation brings to the table is a fresh perspective, especially in the “older” industry of EDA where everyone seems to have 20+ years of experience.

Hannah: I think we bring a fresh perspective on how technology is being used today, especially by those who are just entering the work force, the Generation Y people.

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Granularity and complexity in low power verification

Tuesday, April 2nd, 2013

 

 

Cary Chin, Director of Technical Marketing at Synopsys, has an intriguing take on how to approach verification now that the mandate for design project managers is to meet the low power requirement of the target end-product.   Chin says that if we look at verification in terms of fine and broad “granularity,” users will meet their verification goals with a lot less angst and anguish.    However, at first glance,  I had no idea what Chin was talking about…which is why we asked him to join us and talk about this idea.

 

Ed: Cary,  you’ve been recently talking about granularity in verification, especially in terms of low power.  What does this all mean?  

Cary:  When I think of granularity in low power design, I’m thinking about the size of the “chunks” that we manipulate to improve the energy efficiency (or “low power performance”) of a design.  For example, in most of today’s low power methodologies, large functional blocks are the boundaries we work within – we can shut down these blocks or manipulate the voltage to save energy when peak performance isn’t required.  This boundary level isn’t just a matter of convenience; our tools and methodologies for both implementation and verification can only deal with certain levels of complexity, so we are confined in many dimensions in how we can pursue finer granularity.

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what’s YOUR story?!?!

Monday, March 4th, 2013

In a casual conversational exchange I overheard last week at DVCon (which reminded me of what Steve Jobs said to John Scully –  ”Do you want to sell sugared water for the rest of your life or do you want to…change the world?” –  someone asked if the other’s company wanted to dink out press releases forever or if the company wanted to tell a story that mattered to its audiences.

This conversation got me thinking……There’s nothing wrong with sending out press releases but companies get optimal effect and value when they issue press releases for more than mere information distribution.

What would that be? To reinforce, substantiate or bolster the company’s story. Sending out press releases (or saying, writing or doing any outbound efforts) ought to convey at least one of the company’s message points.

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Predictions 2013 – A Shocker?

Tuesday, February 19th, 2013

 

Our final prediction for 2013 comes from Mike Gianfagna, VP of Corporate Marketing at Atrenta, and prognosticator extraordinaire:

“By the end of 2013, the names of the Big 3 EDA companies will not be the same as they are today.”

 

 

Predictions 2013 – Ravi Ravikumar on Timing and Power

Monday, February 11th, 2013

 

 

 

Today’s prediction comes from Ravi Ravikumar, Vice President of Marketing at ICScape Inc. Ravi, who has over 18 years of experience in marketing, business development & project/program management in the EDA and semiconductor industries, gives his two cents on timing and power closure for 2013…..

 

“If you think timing and power closure were difficult issues at 40 and 28nm, they are going to get worse at 20nm. The traditional means of addressing timing/power closure as a post-implementation step using custom scripts that call on sign-off STA and physical implementation tools to achieve closure is taking too many iterations at 28nm.

As geometries reduce below 28nm, timing/power are more difficult to close due to design-related complex physical requirements, process and manufacturability issues like double/triple patterning and VT cell spacing rules create more R/C effects, impacting timing and power. Power issues in-turn lead to temperature and reliability problems. Design closure becomes a multi-dimensional task.

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