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Posts Tagged ‘EE Times’

HOW will EDA/IP get beyond the horizon?

Sunday, March 16th, 2014

Brian Fuller -­ editor in chief of the now-lamented EE Times during its best years ­- and I were talking about it being great that there are these predictions about where EDA/IP is going in 2014. Chris Rowen’s wrap up prediction talked about EDA’s need to move beyond component – level focus. Chris isn’t alone in this idea.

The question is:  HOW will EDA/IP get beyond the component level and start looking at what’s beyond the 25-year EDA horizon and how EDA can and must add value.

Brian and I would love to hear what readers out there think…..

Does EDA & IP need to go beyond?

Where does it need to go?

And how will it get there?

The Last Word on DAC Themes

Thursday, May 16th, 2013

The final word on the BIG theme(s) for DAC comes from Brian Bailey, Editor of EE Times EDA Designline……

 

For many people, the attendance numbers seem to be the number one issue on their minds this year. DAC has never been to Austin in its 50 year history and only once been to Texas. Yet there is, and has always been, a very large design community in that area, a group of people that have perhaps been overlooked. A head count seems to be a very unimportant number, even though it is an easy metric. But we are an intelligent industry that should know a lot about metrics and I think there are more useful metrics in this case, such as the number of first time attendees.

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New gen view on the passing of print

Monday, April 29th, 2013

 

We old gen folks bemoan the passing of print, even though we (in truth) haven’t cared about print for a number of years – finding the true value being on the web.  I think it’s more symbolic for us old folks than anything else. 

In the wake of the closing of the print editions by UBM, we decided to follow up with the new gen EDA folks we interviewed last week to get their take on this turn of events. 

First up is Hannah Watanabe, of Synopsys, with her thoughts on the news…..

Hannah Watanabe

My mind goes back and forth when it comes to the whole print versus digital media. Personally, when it comes to books, I prefer to have the print version. There is something about turning a page and being able to physically see and feel how many pages I have read and how many I have left. When I’m done with the book, I can put it on a shelf with all of the other books that I have read and feel a sense of accomplishment.

However, when it comes to magazines or monthly or quarterly publications, I much prefer to have access to a digital copy. Unlike books, which I tend to read at home with a cup of tea and a blanket, I find myself looking at magazines and other publications when I’m on the go. When I’m on the go (say waiting for a dentist appointment), I only have bits and pieces of time to read, so it is much nicer to have a digital version or a magazine or publication on my phone than the whole printed version shoved in my purse. So, in short, I think that it is a good and positive move on EE Time’s part to go completely digital. With the age of smartphones, tablets and other mobile devices, I’m sure that the electronic version has a much larger audience and reach. Of course, I do feel for those who are losing their jobs due to a complete migration to digital.

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On Power Awareness in RTL design analysis: Update to a Brian Bailey-designated Top Ten Atrenta article

Wednesday, October 10th, 2012

 

Narayana Koduri’s article on Power Awareness in RTL Design Analysis was the second of two Atrenta articles that EE Times editor Brian Bailey named as the ten most-read contributed articles published in EDA Designline.    Along with number one article Understanding Clock Domain Issues  by Saurabh Verma and Ashima Dabare, Atrenta appears to be the only company with two articles in this top ten list.

So even though his article appeared in July 2012, we asked Narayana to give us an update on what he sees as the power awareness challenges.  Here’s what he had to say.

Ed:  Narayana,   your article sure addressed a hot topic in SoC design. And judging by the readers you got, the design community liked what you had to say.  What can you add to your July 2012 article?

Narayana:  Thanks Ed.   From what I can see, due to aggressive low power requirements, power domains are being implemented in a growing number of SoC designs to reduce both leakage and dynamic power.

Ed:  How so?

Narayana:  UPF or CPF can be used to define the power intent to capture information such as power domains, level shifter requirements, isolation cells, retention cells, power switch cells, etc. These specifications will help implementation tools and verification tools to deal with the power intent properly.

Ed:  So how best to deal with power intent?

Narayana:   RTL tools that verify aspects of the SoC such as clock domain crossings, testability, timing and routing congestion need to be aware of the power intent. If not, the verification is not complete and this may lead to design failures or a costly re-spin of the design. This need for power-aware verification is driving new requirements in the EDA tool flow.

NOTE:  For an update on Understanding Clock Domain Issues see our blog of October 3.

 

 

 

 

Note:  Lee PR does work for Atrenta

 

Top article on EE Times: authors give an update to CDC challenges

Wednesday, October 3rd, 2012

Ashima Dabare

Saurabh Verma

 

 

 

 

 

 

 

On the heels of EE Times editor Brian Bailey naming their article “Understanding clock domain issues” the number one article on EDA Designline, we checked in with authors Saurabh Verma and Ashima Dabare on what they see as developments and new challenges since they wrote their 2007 article. Here’s what they said.

Ed: It appears that your article got twice the number of views as the number two article. Congratulations on the EE Times recognition!

Obviously, CDC was an important design issue in 2007 and it certainly is today. What would you say to designers today?

Ashima: CDC design is evolving and so are the synchronization techniques and verification tools. Since we have written this article we have witnessed new challenges posed to CDC verification tools.

One that comes to mind is evolving synchronization styles. In addition to clever variations of synchronization techniques introduced by designers trying to meet their design objective or schedule, new architectures such as those required for a network on a chip (NoC) have been introduced which in turn require verification tools to re-invent themselves.

Recently CDC tools have introduced generic synchronization verification techniques that do not rely on the structure of the synchronizer and analyze clock domain crossings at the protocol level allowing them to better recognize synchronizers, reduce “noise” and improve root cause analysis.

Saurabh: Also, global chip design dictates blocks and IPs to be designed in various geographical locations. The person doing CDC verification is rarely the designer. CDC verification tools are now challenged with providing root-cause analysis of CDC problems to people who have little knowledge of the block.

I also see as a fact that design size is fast growing and so are the number of clocks and clock domains. Combined with the move toward global chip development, flat CDC verification of large SoCs would be a painful exercise where bugs can easily slip through.

The divide and conquer approach seems to be the best possible approach. To begin with, the lower level blocks should be analyzed and CDC issues, if any, should be fixed at the block level itself. Once all the individual blocks are CDC clean, their abstract models can be plugged in and the complete design can be analyzed for CDC issues at the interconnect level.

Ed: So how would you sum up what CDC design needs in 2012?

Ashima: With the ever increasing complexity of design styles, robust CDC verification is indispensable to enable successful chips in the first silicon attempt!

 

Note:  as near as we can tell, Atrenta is the only company to place two articles in Bailey’s top ten. Narayana Koduri’s Power awareness in RTL design analysis came in as ninth most read. We’ll catch up with him next week, so stay tuned.

 

 

Note: Lee PR does work for Atrenta

Atrenta acquires NextOp – Could this be the start of something BIG?

Wednesday, June 20th, 2012

 

Gary Smith’s statement about the Atrenta acquisition of NextOp has been bandied about this morning in the news….“This could be the start of something big, and NextOp was an excellent place to start.”

See today’s news and analysis about Atrenta’s acquisition of assertion synthesis vendor NextOp plus an interview with Atrenta and NextOp execs in the following online publications:

EDA Café Blog: What Would Joe Do?

EDA Express

EE Daily News

EE Times News & Analysis

EE Times: EDA DesignLine

Gabe on EDA

SemiWiki

System-Level Design

Tech Design Forums

 

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Lee PR does work for Atrenta

ICScape got $28M funding, exhibits for first time at DAC

Friday, May 25th, 2012

 

Named by industry observers as “the biggest EDA company you’ve never heard of” and “a rare and endangered species” of EDA companies, ICScape will bolt out of stealth mode to exhibit at DAC for the first time.

Founded in 2005 by Steve Yang and Jason Xing, the company’s been busy over the last year.  How?  Merging with analog EDA vendor Huada Empyrean Software (HES), getting that US$28M infusion to fund global R&D, customer support and sales expansion, and working on OpenAccess-based product lines that we’ll probably see in some integrated form toward the end of 2012.

ICScape’s booth will greet attendees right at the entrance to the exhibit floor, in Booth 1602.   The company’s executives will be there to:

1)  talk about its technology,

2)  introduce current customers (a major silicon valley Fabless IC company and a major Silicon Valley analog device company) who will also be available at the booth to share firsthand experience,…..and

3)  ensure that ICScape will be one of the EDA names that all of you will have heard of.

See what Paul McLellan,  Mike Demler and  Brian Bailey have to say about ICScape:

http://www.semiwiki.com/forum/content/1248-biggest-eda-company-you-ve-never-heard.html

http://www.eedailynews.com/2012/05/examining-rare-and-endangered-species.html

http://www.eetimes.com/electronics-blogs/other/4372423/New-Companies-exhibiting-at-DAC—ICScape

See you at DAC!

 

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Note:  Lee PR does work for ICScape.

Predictions 2012 – Power Optimization at EDA Forefront, Radiation Tolerance at 28nm

Wednesday, January 25th, 2012

On the ASIC/SoC side of the fence: Reducing power consumption is becoming increasingly important — I anticipate that this is the year that power will finally come to the forefront of EDA tools — I know that they optimize for power now, but largely as a second thought — like synthesis, for example, optimizes first for area and timing and then for power – I think we’ll see a move to optimize for power as a primary consideration.

On the FPGA side of the fence: As we move to the 28nm node and below, radiation is increasingly of concern with regard to electronic devices. It’s no longer just of interest for aerospace applications — at these low device geometries, radiation can affect chips in terrestrial applications. FPGAs are particularly susceptible because in addition to their normal logic and registers and memory cells they also have configuration cells. In the past, the only radiation-tolerant FPGAs were antifuse based — but these are only one-time-programmable (OTP) and trail the leading edge technology node by one or two generations. SRAM-based FPGAs offer many advantages in terms of reconfigurability and being at the leading edge of technology, but they are more susceptible to radiation events in their configuration cells. My prediction is that we will see more and more efforts from FPGA chip vendors and EDA tool vendors with regard to creating radiation-tolerant designs.

On the personal side of the fence: I predict that people will come to realize that what the world needs is a book about creating radiation-tolerant electronic designs that can be read and understood by folks who DO NOT have a PhD in nuclear physics – a book that is of interest to the people who design silicon chips (both analog and digital), the people who create EDA tools, the companies who manufacture the chips, and even software engineers (have you heard of “radiation tolerant software”?). I further predict that someone will finally realize that I am the best person to write this book and will approach me with a really great sponsorship deal that will bring tears of delight to my eyes :-)

Clive “Max” Maxfield
Maxfield High-Tech Consulting
Editor, Programmable Logic DesignLine, EE Times
www.CliveMaxfield.com

 

DesignCon 2011: What was Different?

Friday, February 18th, 2011

turboSo what was different about DesignCon this year? Traffic and make up. There’s a new owner…EE Times.

What else?

1. There were actually people roaming the isles of the exhibit floor! So different from the last several years. It’ll be good to see the DesignCon numbers when EE Times, the new owner of DesignCon, releases them.

2. When I first walked onto the exhibit floor, I was perplexed. Not purely a show for chip designers?  Sure, EDA vendors were there, a couple of IP vendors. But test companies,
connector companies, material companies also!

I asked a couple of people. They acknowledged that the exhibitor make up was different. A couple of the people I polled said that DesignCon had morphed into a systems design or a PCB show. One person thought it had the makings of a complex FGPA design show.

What do y’all out there think?

­ – end ­–

Chip Killers: keeping design managers awake

Monday, February 7th, 2011

Am I gonna make tapeout in time?Liz and I attended a panel at DesignCon that asked the question: what are you doing about the chip killers that delay your tapeout? That’s an intriguing, possibly unanswerable thought, since we’ve asked that question virtually since EDA’s inception. Ed Sperling of Systems-Level Design moderated the panel which had on it: Sunil Malkani of Broadcom, Ravi Damaraju of Juniper, Ramon Macias of NetLogic, John Busco of NVIDIA and Bernard Murphy of Atrenta.

Sperling moderated a lively discussion; questions that he or the panelists or audience posed highlighted the ongoing nature, or unanswerability of the topic. Some were:

• As designers and design managers, what keeps you up at night?

• If your design has to finish in half the time that your previous project took, do you start with a [design methodology and flow] clean slate?

• How do you get hardware and software engineers to work together?

• What’s good enough to get the design out the door?

• How do you define failure?

• What’s the price of failure?

• Who owns quality?

• What do you do when your next project is 4X the size of your last design? Throw people at it? Make the tools do more? Run faster? How?

• How do I turn around a design in a month and get all of these [now-required] apps on it?

• Why does place & route have to be flat?

• When will P&R, timing analysis have to break down the design hierarchically?

• How can verification be improved so that its pessimistic estimates won’t require designers to over-design?

The panelists all bemoaned the dueling standards that plague EDA, attributing them to companies wanting to gain marketing advantage, to the detriment of EDA users.

Sperling will publish a transcript of this panel in a future issue of System-Level Design. Nic Mokhoff published a summary of the panel the next day.

Finally, I have a question: why does DesignCon schedule a management-level panel on a day when the exhibit floor isn’t open? Doesn’t help DesignCon panels’ attendance, which has been paltry for years, seems to me.

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