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Posts Tagged ‘EDA’

Atrenta acquires NextOp – Could this be the start of something BIG?

Wednesday, June 20th, 2012

 

Gary Smith’s statement about the Atrenta acquisition of NextOp has been bandied about this morning in the news….“This could be the start of something big, and NextOp was an excellent place to start.”

See today’s news and analysis about Atrenta’s acquisition of assertion synthesis vendor NextOp plus an interview with Atrenta and NextOp execs in the following online publications:

EDA Café Blog: What Would Joe Do?

EDA Express

EE Daily News

EE Times News & Analysis

EE Times: EDA DesignLine

Gabe on EDA

SemiWiki

System-Level Design

Tech Design Forums

 

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Lee PR does work for Atrenta

Atrenta buys NextOp

Wednesday, June 20th, 2012

 

 

 

 

Atrenta Accelerates Growth in Front End Design with Acquisition of NextOp Software, Inc.

 SpyGlass design productivity enhancements expanded to functional verification for semiconductor and consumer electronics developers

SAN JOSE, Calif — June 20, 2012 — Atrenta Inc., a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries, today announced  that it has acquired NextOp Software, Inc., a leading provider of assertion synthesis technology. Atrenta’s products focus on improving efficiency and reducing cost for the design of complex semiconductor IP and system-on-chip (SoC) devices while NextOp’s products focus on improving efficiency and reducing cost for the functional verification of IPs and SoCs. The combination of both company’s products creates a more complete SoC Realization platform.

The acquisition of NextOp allows Atrenta to expand its de-facto standard SpyGlass® register transfer level (RTL) platform to include functional verification — an important and costly component of advanced SoC design.  Utilizing patented static and formal analysis techniques, the SpyGlass platform currently provides RTL design efficiency improvements in the areas of linting, clock synchronization, power optimization, testability, timing constraints and physical routing congestion. The SpyGlass platform will now be expanded to include functional verification support using NextOp’s patented dynamic assertion synthesis technology, resulting in verification efficiency improvements for semiconductor and consumer electronics developers.

“The addition of NextOp’s functional verification technology will give our customers a distinct advantage by providing complete coverage of front end design activities,” said Dr. Ajoy Bose, chairman, president and CEO of Atrenta. “Atrenta’s customers have come to rely on SpyGlass to verify a broad range of design intent, but functional verification was a missing part of our platform. NextOp’s assertion synthesis completes this part of our offering – Atrenta customers will now have added confidence that their designs will work as expected while meeting schedule and performance requirements. We are very excited to bring these innovative solutions and the resulting expanded benefits to our large customer base. ”

“Atrenta is one of the largest private EDA companies,” said Dr. Yunshan Zhu, president and CEO of NextOp Software.  “NextOp has pioneered assertion synthesis technology. Our tool is now widely deployed in production at multiple tier 1 customers – many of whom also use SpyGlass. Atrenta’s world-class field operation will further accelerate the mainstream adoption of assertion synthesis.”

“I’ve heard good things about NextOp’s verification technology from some impressive customers – the combination of Atrenta’s RTL design and NextOp’s RTL verification technology will improve the entire SoC Realization process,” said Jim Hogan, EDA industry veteran and private investor. “I’m also glad to see private/private acquisitions like this happening again after such a long dry spell. Atrenta could be leading a trend in renewed growth for the EDA sector.”

“With the acquisition of Magma there has been renewed talk about a roll-up in the middle of the EDA community,” saidGary Smith, founder and chief analyst for Gary SmithEDA.  “The most obvious candidates are the RTL sign-off tool vendors, and the most talked about driver, of the roll-up, has been Atrenta.  This could be the start of something big, and NextOp was an excellent place to start.”

NextOp’s BugScope assertion synthesis tool will be sold and supported by the combined Atrenta/NextOp worldwide field organization. Dr. Yunshan Zhu will assume the role of vice president, new technologies reporting to Dr. Ajoy Bose. Dr. Yuan Lu, co-founder and CTO of NextOp will assume the role of chief verification architect reporting to Dr. Zhu.  Financial terms of the transaction were not disclosed.

About Assertion Synthesis

Assertion synthesis leverages design and test bench information to automatically generate high quality assertions and functional coverage properties.  Generating assertions and coverage properties manually is tedious and error-prone. Assertions represent a machine-readable version of design intent and are used to improve verification completeness. Functional coverage properties identify functional coverage deficiencies providing guidance for verification teams. When used together, design teams can reduce functional verification time and improve overall functional coverage, resulting in lower design costs, better first-time silicon success and improved quality.

About Atrenta

Atrenta’s SpyGlass® Predictive Analysis software platform significantly improves design efficiency for the world’s leading semiconductor and consumer electronics companies. Patented solutions provide early design insight into the demanding performance, power and area requirements of the complex system on chips (SoCs) fueling today’s consumer electronics revolution. More than two hundred companies and thousands of design engineers worldwide rely on SpyGlass to reduce risk and cost before traditional EDA tools are deployed. SpyGlass functions like an interactive guidance system for design engineers and managers, finding the fastest and least expensive path to implementation for complex SoCs.  SpyGlass from Atrenta: Insight. Efficiency. Confidence.   www.atrenta.com

About NextOp Software

NextOp Software, Inc. is focused on delivering assertion-based verification solutions that allow design and verification teams to uncover bugs, expose functional coverage holes, and increase verification observability. NextOp’s BugScope assertion synthesis is the first product to automatically generate whitebox assertions and functional coverage properties in SVA, PSL and Verilog formats. BugScope’s properties are used to drive progressive, targeted verification via robust, executable design specifications for existing simulation, formal and emulation flows. The company is headquartered at2900 Gordon Avenue, Suite 100,Santa Clara,CA95051. For more information, visit www.nextopsoftware.com or call +1 408-830-9885.

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© 2012 Atrenta Inc. All rights reserved. Atrenta, the Atrenta logo and SpyGlass are registered trademarks of Atrenta Inc. BugScope and NextOp are trademarks of NextOp Software, Inc. All others are the property of their respective holders.

This press release contains forward-looking statements. Atrenta disclaims any obligation and does not undertake to update or revise the forward-looking statements in this press release.

 

 

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Lee PR does work for Atrenta

 

Three rules to get greatest value from your IP libraries: Migration Migration Migration! Sagantec’s CEO talks to Luke Collins

Tuesday, June 12th, 2012

 

 

Luke Collins, editor, Tech Design Forums, talks with Sagantec CEO, Coby Zelnik, and CTO, Marten Berkens, about migration technology.

 

http://www.techdesignforums.com/blog/2012/06/05/dac2012-sagantec-offers-lifebelt-to-28nm-users-path-to-20nm-libraries/

 

 

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Note:  Lee PR does work for Sagantec

The SpyGlass® value interviews

Friday, June 1st, 2012

 

 

Atrenta has pulled together quite a slate of customers, partners, an industry observer and EDA’s premier investor to talk about the value SpyGlass brings to each of their realms. It’ll be interesting to hear how this signature product has proliferated in different environments! Atrenta invites you to stop by and hear how SpyGlass improves productivity @ Xilinx, Vivante, Sonics and Arteris and why Dan Nenni and Jim Hogan see SpyGlass as the consummate ubiquitous product in EDA.

The talks will be held at Atrenta’s booth #2230.

Monday, June 4

9:30 am…..Jack Browne, Sonics
10:30 am…Frederic Rivoallon, Xilinx
2:00 pm…..Halim Theny, Vivante

Tuesday, June 5

10:30 am…Charlie Janac, Arteris
2:00 pm…..Frederic Rivoallon, Xilinx
3:00 pm…..Dan Nenni, SemiWiki
5:00 pm…..Jack Browne, Sonics

Wednesday, June 6

10:30 am…Charlie Janac, Arteris
12:30 pm…Jim Hogan

……………………….

 
Note: Lee PR does work for Atrenta

ICScape got $28M funding, exhibits for first time at DAC

Friday, May 25th, 2012

 

Named by industry observers as “the biggest EDA company you’ve never heard of” and “a rare and endangered species” of EDA companies, ICScape will bolt out of stealth mode to exhibit at DAC for the first time.

Founded in 2005 by Steve Yang and Jason Xing, the company’s been busy over the last year.  How?  Merging with analog EDA vendor Huada Empyrean Software (HES), getting that US$28M infusion to fund global R&D, customer support and sales expansion, and working on OpenAccess-based product lines that we’ll probably see in some integrated form toward the end of 2012.

ICScape’s booth will greet attendees right at the entrance to the exhibit floor, in Booth 1602.   The company’s executives will be there to:

1)  talk about its technology,

2)  introduce current customers (a major silicon valley Fabless IC company and a major Silicon Valley analog device company) who will also be available at the booth to share firsthand experience,…..and

3)  ensure that ICScape will be one of the EDA names that all of you will have heard of.

See what Paul McLellan,  Mike Demler and  Brian Bailey have to say about ICScape:

http://www.semiwiki.com/forum/content/1248-biggest-eda-company-you-ve-never-heard.html

http://www.eedailynews.com/2012/05/examining-rare-and-endangered-species.html

http://www.eetimes.com/electronics-blogs/other/4372423/New-Companies-exhibiting-at-DAC—ICScape

See you at DAC!

 

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Note:  Lee PR does work for ICScape.

Atrenta’s unified platform

Tuesday, May 15th, 2012

Maybe Atrenta is saying goodbye to the thought-bubble guy…..

Atrenta’s SpyGlass has always been the dominant name in the company’s brand portfolio,and for good reason. It’s the dominant product in RTL design analysis, verification and optimization.

Now, Atrenta is reconfiguring its product lineup to formalize this state of affairs. SpyGlass now becomes the unifying platform for all Atrenta products.  Sort of the mother ship that all Atrenta products are based on.

So what’s a unified platform? All the tools now share a common set up and debugging methodology and tighter GUI. And what can users verify and optimize from this new unified platform? Syntax, power, testability, clock synchronization, timing and routing congestion. All at the RTL stage, well before detailed implementation begins.

(more…)

3D in Monterey Next Week

Thursday, March 29th, 2012

 

This event is happening next week! Worth signing up if you can get down
there!………

 

EDPS is coming up again!  It’ll be held April 5-6, 2012 at the Monterey Beach Hotel in Monterey California.

This year, the 3D topic will be the focus of day two.

First and foremost,  Riko Radojcic, director of engineering at Qualcomm, will be talking about the 3D IC roadmap as the keynote speaker on day two.   (see his views on 3D standards:  http://www10.edacafe.com/blogs/ed-lee/2011/04/11/riko-radojcic-on-3d-standards/

Following the 1-hour keynote will be four 1/2 hour talks on various specific 3D-related topics:

* Stephen Pateras of Mentor on BIST for 3D ICs

* Arif Rahman of Altera on FPGA design challenges, presumably 3D ones

* Marc Greenberg of Cadence on the wide-IO standard for putting memory stacks on processors

* Sandeep Goel of TSMC and Bassilios Petrakis of Cadence on an end-to-end test flow for 3D IC stacks

Then there’s a lunch panel on 3D, moderated by Steve Leibson of Cadence,  with these panelists addressing: The short-, medium and long-term path to the 3D Ecosystem.

* Herb Reiter

* Samta Bansal of Cadence

* Dusan Petranovic of Mentor

* Deepak Sekar of Monolithic 3D

* Steve Smith of Synopsys

* Phil Marcoux of PPM Associates

Herb is arguably the primary 3D observer and advocate on what technologies have to be in place to handle the upcoming 3D challenge that’s starting to hit designers now.

John Swan is the General Chair of EDPS 2012. Herb Reiter is the Session Chair for the keynote, four shorter presentations and the panel discussion during  “3D Day”, Friday, April 6.

Very worthwhile to attend if you can get the time off.

Turning the tables on Graham Bell

Tuesday, March 27th, 2012

 

All of us in EDA know and know of Graham Bell, head honcho of EDA Café and notorious video chronicler of EDA. Liz and I often wonder, “who hasn’t Graham interviewed on video?”

Well, we were able to grab the microphone (after a little jostling for the mike) and camera and ask Graham what he thought was happening in EDA and with EDA media these days.

Here’s what he had to say.

3D in Monterey

Thursday, March 22nd, 2012

EDPS is coming up again!  It’ll be held April 5-6, 2012 at the Monterey Beach Hotel in Monterey California.

This year, the 3D topic will be the focus of day two.

First and foremost,  Riko Radojcic, director of engineering at Qualcomm, will be talking about the 3D IC roadmap as the keynote speaker on day two.   (see his views on 3D standards:  http://www10.edacafe.com/blogs/ed-lee/2011/04/11/riko-radojcic-on-3d-standards/

Following the 1-hour keynote will be four 1/2 hour talks on various specific 3D-related topics:

* Stephen Pateras of Mentor on BIST for 3D ICs

* Arif Rahman of Altera on FPGA design challenges, presumably 3D ones

* Marc Greenberg of Cadence on the wide-IO standard for putting memory stacks on processors

* Sandeep Goel of TSMC and Bassilios Petrakis of Cadence on an end-to-end test flow for 3D IC stacks

Then there’s a lunch panel on 3D, moderated by Steve Leibson of Cadence,  with these panelists addressing: The short-, medium and long-term path to the 3D Ecosystem.

* Herb Reiter

* Samta Bansal of Cadence

* Dusan Petranovic of Mentor

* Deepak Sekar of Monolithic 3D

* Steve Smith of Synopsys

* Phil Marcoux of PPM Associates

Herb is arguably the primary 3D observer and advocate on what technologies have to be in place to handle the upcoming 3D challenge that’s starting to hit designers now.

John Swan is the General Chair of EDPS 2012. Herb Reiter is the Session Chair for the keynote, four shorter presentations and the panel discussion during  “3D Day”, Friday, April 6.

Very worthwhile to attend if you can get the time off.

Predictions 2012 – Persistence of Memory

Thursday, February 9th, 2012

To finish off our series of predictions, I would like to point you to another series of interesting and informative prophesies.  Click on the following topics to see these predictions collected by Brian Bailey, Editor of EDA DesignLine.

Industry Trends

Tools

ESL

IP and Physical Design

The Bold Prediction for EDA

 

A big THANK YOU from Ed & me (Liz) to all who shared their eye opening predictions with us.  Click on their names to see their predictions.  Mike Gianfagna, Karen Bartleson, Paul McLellan, Jens Andersen, Bob Smith, Steve Schulz, Mathias Silvant, Herb Reiter, Max Maxfield, Chris Edwards, John Barr.

 

Only time will tell……

 

The Persistence of Memory, 1931, Salvador Dali

 

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