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Posts Tagged ‘EDA’

EDA will auction some really cool stuff

Monday, September 30th, 2013

 

There’s an EDA industry reunion at the Computer History Museum on October 16th. “EDA: Back to the Future” is being put on by EDAC along with several sponsors, and it looks like it will be a night to remember.  To learn more about the event and purchase tickets click here.

Part of this event is a fund raising auction.  I recently talked with Mike Gianfagna at Atrenta about the auction to understand what that part is all about.

 

Ed: Mike, I understand that part of the event on October 16th is a fund raising auction.  Can you tell me a little about that?

Mike:  Sure Ed. The Computer History Museum is working on an exhibit for EDA – one that captures the rich history of this industry and preserves some of its innovation in the form of physical artifacts and some of its pioneers in the form of oral histories, captured on video. It’s a terrific project, but we need money to keep the progress going. The auction on the evening of October 16th is focused on raising that money.

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The RTL signoff conversation goes to Asia

Wednesday, August 28th, 2013

 

Atrenta will discuss what RTL signoff requirements are needed for SoC designers in China, South Korea and Taiwan at their upcoming seminars in September and October.

Click here for more information.

 

 

 

 

 

 

LPR does work for Atrenta

How to avoid timing exception pitfalls

Tuesday, August 20th, 2013

We often think that we’ve got the timing job nailed down and that there aren’t any problems that we can’t easily, almost routinely solve.  Using timing exceptions to optimize synthesis or P&R shouldn’t be a problem.

However, making an error when specifying timing exceptions can possibly shut down a design project.

Take a look at what Atrenta’s Shaker Sarwary, Ramesh Dewangan and Sridhar Gangadharan say about how to avoid this situation:

http://alturl.com/99bbs

(Note:  white paper download requires registration)

LeePR does work for Atrenta.

 

Webinar on ESL presented by Gary Smith

Tuesday, August 13th, 2013

 

Do you want to know the latest on ESL?  Curious what today’s tools look like?

Gary Smith will be conducting a webinar this coming Monday on this very topic – ESL – are you Ready?

Gary, along with Mike Gianfagna of Atrenta and Jason Andrews and Frank Schirrmeister of Cadence, will examine the evolution of ESL over the past few years and share the breakthroughs that have occurred in the flow.

When is it?

11:00-11:45 am PDT

Monday, August 19, 2013

Gary will be recognizing the industry’s “ESL Heroes.”  Want to know what an ESL Hero is?  Tune in Monday to find out.

You can register for the webinar here.

The Semiconductor Supply Chain Tomorrow

Monday, August 12th, 2013

Before the summer ends and the summer blockbuster movies and DAC become a distant memory (still shaking my head over The Lone Ranger’s flop), let me just share Mike Gianfagna’s vision for next summer’s blockbuster.

It’s a tad more like Terminator 2 than the masked man and Tonto.  And it may not be too far from reality – that’s what’s exciting…..and scary.

Of course it’s about the semiconductor supply chain and how it might affect our lives in the future.

 

Click here to look into the future.

~ Liz

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Kickin’ it up in Austin with Ajoy and Wally

Friday, June 28th, 2013

For some Friday fun….

For those of you who were unable to attend the big 50th DAC party, or you just missed the intro to Asleep at the Wheel, you might find this little video entertaining.

It’s a video of Cowboy Ajoy and Ranger Rhines (aka Ajoy Bose, CEO of Atrenta and Wally Rhines, CEO of Mentor), cutting it up on the Austin City Limits stage to kick off Kickin’ it up in Austin.

Design Rule Manual Creation a Bottleneck?

Monday, June 24th, 2013

Sage Design Automation, Inc. announced its founding technology last month and created a lot of customer and media buzz at DAC’13 inAustin.  I bet a lot of people were surprised that design rule manual creation and DRC deck implementation were manual, error-prone  tasks – especially as we get into smaller process geometries – and that they can take years to put one together.

In a way, it’s a lot like writing a long paper on a typewriter, or even by hand.  When you make an error, you use White Out (remember that?) or type back over the error with the erasing ribbon.  There’s no way to correlate the paper’s index, spell check, grammar check or check for consistency.

So we accosted Sage-DA president and CEO Coby Zelnik to ask him about this problem, one that many of us assumed just took care of itself!  Here’s what he had to say.

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The Internet of Things

Sunday, June 16th, 2013

 

As Mike Demler predicted back in May, the “Internet of Things” was all the buzz at DAC this year. 

Freescale CEO Gregg Lowe talked about the opportunities and challenges in his keynote.  

Mentor CEO Wally Rhines said in his keynote that the big growth in the semiconductor industry will come with the Internet of Things. 

It was simultaneously discussed at the GSA European Executive Forum in Munich and the Sensors Expo in Chicago

What do you think? 

Is it the next big thing? 

Can EDA step up to the challenge? 

And what does it mean to our future?

Warren Savage interviews Mike Gianfagna on the importance of collaboration

Sunday, June 2nd, 2013

In the following video, Warren Savage, CEO of IPextreme, talks with Mike Gianfagna, VP of Corporate Marketing at Atrenta, about collaboration – with TSMC and the Constellations partners.

Mike’s dream is for “a vibrant industry with a well-defined quality metric.”

Lee PR does work for Atrenta

IP exerting its presence at DAC

Monday, May 20th, 2013

 

With less than 3 weeks away until DAC’13, Liz and I asked Warren Savage about  IPextreme’s  and Constellations’ planned presence there.  Warren is not only founder and CEO of IPextreme, but also head of the IP consortium, Constellations.

We caught up with Warren recently, and Mike Gianfagna, VP of Corporate Marketing at Atrenta (Atrenta is a Constellations partner), happened to be there.  So, the two of them let us in on what Constellations would be up to at DAC.

 

Liz: Warren, what play does IP have at DAC this year?

Warren Savage
President and CEO
IPextreme

Warren: Change is slow, but IPextreme and Constellations are happy to report change is afoot and our workshop at DAC serves as a prime example of this. Together with TSMC and our Constellations partners Atrenta and Sonics, we are pleased to present “Driving Quality to the Desktop of the DAC Engineer” on Sunday, June 2 from 1:00 to 5:00 PM. This workshop showcases a foundry, two IP companies, and an EDA company working together—exactly as we do every day.

Why, then, is this the first DAC workshop of its kind? Why have the ties binding us together in the semiconductor ecosystem not been highlighted before? Perhaps the old saying, “If all you have is a hammer, everything looks like a nail,” is the only explanation. At the end of the day, our customers need all of us – both IP providers and EDA vendors. We owe it to them not only to recognize that, but also to make their lives easier by working together.

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DownStream: Solutions for Post Processing PCB Designs
S2C: FPGA Base prototyping- Download white paper



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