Posts Tagged ‘EDA & IP’
Monday, February 17th, 2014
Next up in our series of predictions is the astute insight of Mike Demler, Senior Analyst with The Linley Group & MICROPROCESSOR report, and former EDA & Chip Design news analyst.
“It’s all about the ecosystem triad: EDA + foundry + IP. Cadence and Synopsys continue to evolve more in the IP direction, and there is really not much to say about the tools that hasn’t been said for a long time —just make it all work together! Redundant “standards” and artificial barriers to interoperability cost the semiconductor industry by lowering productivity. This is the problem with the disaggregated model. Back in the days when “real men” had fabs, companies could develop complete design flows without such obstacles.
The triad needs to work together to get over the stall inMoore’s Law at 28nm. Foundries are incurring delays in getting to 16/14nm FinFETS, and almost nobody is going to use 20nm. The chip industry needs an overall lower-cost solution in order to make sub-28nm processes economically viable. Forget 3D ICs, those will be niche products for a long time, about as popular as 3D TV.
Wednesday, February 12th, 2014
Bryon Moyer, Technology Editor at EE Journal, weighs in on what the chip industry needs from EDA and IP in 2014.
“At the low level, this is going to be the year where the push and pull between EDA companies and users determines how easy FinFETs are to design with.
At the high level, it feels to me like IP and EDA need to come closer together. For years, logic design has been done using text because higher-level languages allow better design abstraction and productivity for hand-crafted designs than prior schematic approaches did. When IP entered the scene, designs were mostly hand-done, with occasional bits farmed out to IP. But now IP dominates, whether internal or third-party. Rather than having a custom-logic paradigm that accommodates IP, it feels like we need to move more to an IP paradigm that accommodates custom logic. And it’s not just about logic either: mixed signal is everywhere, and should be included more seamlessly.”
Thursday, February 6th, 2014
Anindya Saha, Associate VP (VLSI) at Saankhya Labs, shares his insights on what EDA and IP vendors need to do for their users in 2014.
“Today the EDA and IP companies alike are in the race to cater to the big semiconductor players by offering the greatest IP in the latest process geometries. However, semiconductor startups, – such as Saankhya – do not change process nodes very quickly because it may not necessarily make business sense. Here is why.
‘Process design margins’ is a fact of life, which we need to add when we use the latest process nodes. Incorporating these design margins simply adds to the overall SoC design cycle time which we want to keep to a minimum. Hence staying with the older process nodes may be a more prudent choice. When we look at the IP domain, we can categorize the available IPs into the following buckets – Analog IPs, Standard Cell and Memory IPs, Processor Soft Cores and Connectivity IPs. Besides the usual PPA (Power, Performance and Area) metrics, what we look at for each of these categories is the metric of Power Efficiency. This metric can be based on mW/Mhz or in some cases mW/sq. mm depending on the kind of tradeoffs which we intend to do at System level.
The following are some of the issues I feel EDA and IP companies should address, especially in the domain of standard cell and memory IPs which are commonly used in almost all ASIC Designs today. (more…)
Monday, February 3rd, 2014
Robert Beanland, Senior Director, Corporate Marketing at Atrenta, weighed in on what EDA and IP vendors need to do in 2014.
“Ahhh, the age old question of, ‘What does EDA and IP need to do this year?’ Well, …
The IP folks need a way to provide fully validated IP to their customers with not only a good understanding of all the validation that has been done, but also the expected use model and configurations for the IP. The use model is critical because it is quite common for IP to be ‘abused’ in a way or mode that the IP vendor never expected. When this happens, the customer must be able to assess the problem in-situ and work with the IP vendor to find a resolution. A standardized quality metric is much more desirable than the current option of comparing each vendor’s unique assessment of their validation. This validation and analysis should include, but is not limited to, power, clock domains, testability and physical. The ‘clean’ IP can then be used with more confidence by their customers in their SoC integration.
Monday, January 27th, 2014
We asked Mike Gianfagna, VP of Marketing at eSilicon and former VP of Corporate Marketing at Atrenta, about EDA, IP and the chip industry in 2014.
Ed: What does EDA and IP need to do in 2014?
Mike: Work more effectively with each other. IP integration continues to be a huge bottleneck for SoC design. A more uniform quality metric and a way to enforce it is desperately needed. This problem can’t be solved in isolation. EDA and IP companies need to collaborate to tame this issue. They can do it.
Ed: What does the chip industry want from EDA and IP in 2014?
Mike: The same thing really. Every SoC project is dependent on somebody’s IP. Whether it’s internally supplied or provided by your favorite IP supplier or your favorite ASIC supplier, the requirement for easy integration with no surprises is the same. Better collaboration between members of the SoC supply chain will definitely help.
Sunday, January 19th, 2014
Next up in our series of 2014 forecasts we have the sage predictions of Angel Orrantia, Business Development Director at SKTA Innopartners LLC….
“Aside from some massive players, the rest of the chip industry has been forced to adopt capital light business models. Simultaneously, we’re seeing the mask costs making advanced nodes prohibitively expensive.
Wednesday, August 28th, 2013
Atrenta will discuss what RTL signoff requirements are needed for SoC designers in China, South Korea and Taiwan at their upcoming seminars in September and October.
Click here for more information.
LPR does work for Atrenta
Wednesday, February 1st, 2012
In 2012, we’ll see tablets and smartphones changing the world. That’s another way of saying Apple’s moves will have huge implications in semiconductors, foundries and EDA.
Apple’s use of the Samsung foundry has started an arms race between Samsung, TSMC and Global Foundries. Samsung is ramping up to meet the capabilities and capacity of TSMC. Intel is being pushed to stay ahead technologically and to consider new business models. Global Foundries continues to work to ramp its yields.
This situation will be good for semiconductor equipment and EDA vendors as well. Their tools will facilitate the new processes and the link between design and manufacturing.
Another element: in 2012, we’ll see the supply chain continue to consolidate. Why? The cost to design a complex SoC requires a big budget and a big market opportunity. Only the largest of semiconductor companies can tackle these designs. This increasing cost helps the FPGA vendors.
The foundries face increasing technology and capital requirements to move to new process nodes. Only a few will make it.
The public markets have been closed to EDA companies for a number of years making acquisition the most likely exit for EDA startups. Apache chose to be acquired by Ansys in 2011. It has been difficult for a new, large EDA competitor to emerge. This bodes well for Big EDA in its negotiations with Big Foundry and Big Semiconductor. In 2012 I believe there are several EDA companies poised to go public.
Who will be the beneficiary of these changes in 2012? Apple. Consumers should also benefit as new, leading edge fab capacity will be used to make exciting new devices.
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Monday, January 30th, 2012
The main technical breakthroughs we can expect this year will probably revolve around double patterning in lithography as EDA companies try to optimize the technique for density and performance. And it will probably have knock-on effects way up in the design flow, forcing designers to adopt much more regular designs. But, unless EUV sees a major breakthrough, double and further levels of multiple patterning is something people will need to get used to.
Regularity is likely to become a feature of low-power design as well. Although it hurts effective density, the drive to cut power consumption will see much more use made of on-chip redundancy – we’ve already seen some of that in the nVidia Tegra 3 and the ARM Big.Little initiative. We could see those techniques begin to extend into ultralow power circuits using near or subthreshold devices as engineers discover how to model circuits effectively and recover lost performance at very low voltages. Some of these techniques will also help reinvigorate older processes – using better EDA to trim power consumption instead of relying primarily on process changes to deliver better energy efficiency.
Technology writer: Engineering & Technology, New Electronics, Low-Power Design Blog, Tech Design Forums