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Posts Tagged ‘design closure’

Predictions 2013 – Ravi Ravikumar on Timing and Power

Monday, February 11th, 2013

 

 

 

Today’s prediction comes from Ravi Ravikumar, Vice President of Marketing at ICScape Inc. Ravi, who has over 18 years of experience in marketing, business development & project/program management in the EDA and semiconductor industries, gives his two cents on timing and power closure for 2013…..

 

“If you think timing and power closure were difficult issues at 40 and 28nm, they are going to get worse at 20nm. The traditional means of addressing timing/power closure as a post-implementation step using custom scripts that call on sign-off STA and physical implementation tools to achieve closure is taking too many iterations at 28nm.

As geometries reduce below 28nm, timing/power are more difficult to close due to design-related complex physical requirements, process and manufacturability issues like double/triple patterning and VT cell spacing rules create more R/C effects, impacting timing and power. Power issues in-turn lead to temperature and reliability problems. Design closure becomes a multi-dimensional task.

(more…)

ICScape got $28M funding, exhibits for first time at DAC

Friday, May 25th, 2012

 

Named by industry observers as “the biggest EDA company you’ve never heard of” and “a rare and endangered species” of EDA companies, ICScape will bolt out of stealth mode to exhibit at DAC for the first time.

Founded in 2005 by Steve Yang and Jason Xing, the company’s been busy over the last year.  How?  Merging with analog EDA vendor Huada Empyrean Software (HES), getting that US$28M infusion to fund global R&D, customer support and sales expansion, and working on OpenAccess-based product lines that we’ll probably see in some integrated form toward the end of 2012.

ICScape’s booth will greet attendees right at the entrance to the exhibit floor, in Booth 1602.   The company’s executives will be there to:

1)  talk about its technology,

2)  introduce current customers (a major silicon valley Fabless IC company and a major Silicon Valley analog device company) who will also be available at the booth to share firsthand experience,…..and

3)  ensure that ICScape will be one of the EDA names that all of you will have heard of.

See what Paul McLellan,  Mike Demler and  Brian Bailey have to say about ICScape:

http://www.semiwiki.com/forum/content/1248-biggest-eda-company-you-ve-never-heard.html

http://www.eedailynews.com/2012/05/examining-rare-and-endangered-species.html

http://www.eetimes.com/electronics-blogs/other/4372423/New-Companies-exhibiting-at-DAC—ICScape

See you at DAC!

 

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Note:  Lee PR does work for ICScape.

CST: Webinar series



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