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Posts Tagged ‘Chip Design’

How to get to soft IP quality

Wednesday, November 7th, 2012

What is soft IP quality and why should we care?

What are the challenges in managing semiconductor IP?

How can we solve IP reuse integration?

If you’d like to know the answers to these questions and others, check out this presentation by Michael Johnson of Atrenta from the Constellations 2012 conference.

Johnson succinctly defines soft IP quality and proposes a way for the industry to get to a soft IP quality standard.

 


 

 

Note:  Lee PR does work for Atrenta

 

 

Who’s getting hit by the double whammy of verification?

Thursday, October 25th, 2012

 

Piyush Sancheti

In a recent article written by EDA industry watcher Ann Steffora Mutschler, Atrenta’s VP of Product Marketing Piyush Sancheti pointed to the curse of the verification double whammy for engineers:

“For verification engineers and for designers, this is a double whammy,” noted Piyush Sancheti, vice president of product marketing at Atrenta. “If you ask a digital design or digital verification team, they will tell you that low-power design and the introduction of analog/mixed-signal components on what used to be a simple digital chip is a significant verification challenge. For verification engineers what this means is your finite state machines or your control logic just got that much more complicated. If you go from 2 domains to 20 domains, your verification complexity just increased an order of magnitude.”

We caught up with Piyush in the Atrenta hallway and asked him to elaborate on his statement.  Here’s what he said:

Ed:   So what is the double whammy and why should we care?

Piyush: With the onset of A/MS and low power requirements, digital design teams now have to contend with two new foreign entries to their previous monolithic design environment.

Ed:  And they are…?

Piyush:  New logic blocks that are completely foreign to digital designers and the implementation of power management techniques like power & voltage domains. Voltage domains allow the timing critical portions of the design at a higher voltage (overdrive), and the rest at a lower voltage (underdrive). Power domains, on the other hand, allow one to turn off the power on entire blocks of the design when not in use.

Ed:  Haven’t digital designers always needed to be conscious and conscientious about power?

Piyush:  Not to the extent they must be these days.    Here’s the challenge – say you are designing a chip for a smart phone.  When you are watching a YouTube video, you don’t need the phone function, so you want to make sure that the phone functions are off.  What’s the result?  You’re saving power, or in consumer terms, preserving battery life.   But, if the smart phone gets a call, you have to be sure the phone function turns on instantly, without adversely impacting your video viewing experience.  So designers have to make sure the domains turn off and on in perfect harmony, almost like conducting a symphony.

So what’s the problem?  New power management logic that designers are not used to has been thrust on them rapidly and recently.  They need to get up to speed fast.  This is not an easy job. Not only that, but you now have very complex finite state machines that switch these functions on and off seamlessly.

Ed:  So what’s the solution?

Piyush:   A comprehensive methodology for functional and structural verification.

Ed:  Can you elaborate?

Piyush:  These complex finite state machines must be verified exhaustively for functional correctness. You need to make sure that the various functions on your smart phone wake up and shut off in a timely manner without adversely impacting the device behavior, and ultimately the user experience. With structural verification you need to make sure that the perimeter of the voltage and power domains are properly secured. When you have signals crossing one voltage domain to another, you need voltage level shifters. Similarly, you need isolation logic between power domains, to ensure that signals don’t float to unknown values when a domain is powered off.

Ed:  So what sort of tools and methodologies do you see out there to meet the double whammy challenge?

Piyush:  Well, of course, I’m most familiar with the Atrenta platform.   There are undoubtedly other ways to go about this job.  But from what I see, SpyGlass Power is being used by many large chip and system companies for static signoff of power and voltage domains. SpyGlass Advanced Lint enables exhaustive finite state machine verification using formal techniques. And with our recent acquisition of NextOp Software, we now have BugScope to ensure dynamic verification (simulation) is covering all the corner cases that are now part of your design because of this increased complexity.

Ed:  So your final words of wisdom?

Piyush:  Verification of modern day SoC designs is a daunting task. But like any complex problem a systematic approach using a combination of static and dynamic verification techniques will help you reach your device ambitions faster.

 

 

 

–        Note:  Lee PR does work for Atrenta.

Top article on EE Times: authors give an update to CDC challenges

Wednesday, October 3rd, 2012

Ashima Dabare

Saurabh Verma

 

 

 

 

 

 

 

On the heels of EE Times editor Brian Bailey naming their article “Understanding clock domain issues” the number one article on EDA Designline, we checked in with authors Saurabh Verma and Ashima Dabare on what they see as developments and new challenges since they wrote their 2007 article. Here’s what they said.

Ed: It appears that your article got twice the number of views as the number two article. Congratulations on the EE Times recognition!

Obviously, CDC was an important design issue in 2007 and it certainly is today. What would you say to designers today?

Ashima: CDC design is evolving and so are the synchronization techniques and verification tools. Since we have written this article we have witnessed new challenges posed to CDC verification tools.

One that comes to mind is evolving synchronization styles. In addition to clever variations of synchronization techniques introduced by designers trying to meet their design objective or schedule, new architectures such as those required for a network on a chip (NoC) have been introduced which in turn require verification tools to re-invent themselves.

Recently CDC tools have introduced generic synchronization verification techniques that do not rely on the structure of the synchronizer and analyze clock domain crossings at the protocol level allowing them to better recognize synchronizers, reduce “noise” and improve root cause analysis.

Saurabh: Also, global chip design dictates blocks and IPs to be designed in various geographical locations. The person doing CDC verification is rarely the designer. CDC verification tools are now challenged with providing root-cause analysis of CDC problems to people who have little knowledge of the block.

I also see as a fact that design size is fast growing and so are the number of clocks and clock domains. Combined with the move toward global chip development, flat CDC verification of large SoCs would be a painful exercise where bugs can easily slip through.

The divide and conquer approach seems to be the best possible approach. To begin with, the lower level blocks should be analyzed and CDC issues, if any, should be fixed at the block level itself. Once all the individual blocks are CDC clean, their abstract models can be plugged in and the complete design can be analyzed for CDC issues at the interconnect level.

Ed: So how would you sum up what CDC design needs in 2012?

Ashima: With the ever increasing complexity of design styles, robust CDC verification is indispensable to enable successful chips in the first silicon attempt!

 

Note:  as near as we can tell, Atrenta is the only company to place two articles in Bailey’s top ten. Narayana Koduri’s Power awareness in RTL design analysis came in as ninth most read. We’ll catch up with him next week, so stay tuned.

 

 

Note: Lee PR does work for Atrenta

Why should we care about IP quality?

Monday, September 10th, 2012

Piyush Sancheti

 

 

Why can 3rd party IP impede a design getting to tapeout?  Why is IP reuse costing design projects more time and effort?  And what can we do about it?  Piyush Sancheti, VP of Product Marketing at Atrenta,  explores these issues and answers some of these questions in the viewpoint below on the GSA IP Working Group blog:

 

http://www.gsaglobal.org/2012/08/general-working-group-activity-recruiting-meeting-locations-updates-agendas/

 

Lee PR does work for Atrenta

Ajoy Bose and Jim Hogan on the systems customers now defining SoC design

Tuesday, September 4th, 2012

 

Jim Hogan

Ajoy Bose

 

 

 

 

 

 

 

Atrenta CEO Ajoy Bose and EDA visionary and investor Jim Hogan spoke at a recent National Institute of Technology (NIT) meeting on the momentous changes we see in who controls chip design these days. Clearly, systems companies like Apple define – even dictate – what they want from their silicon vendors..and these systems customers certainly want a lot more than they did ten years ago.

Jim tells us why we have to care:

Video Part 1

Video Part 2

Power Point Presentation

Ajoy shows us how to care:

Video Part 1

Video Part 2

Power Point Presentation

 

 

 

 

 

Lee PR does work for Atrenta

Renesas on SpyGlass Physical

Monday, August 20th, 2012

 

 

Yasushi Ozaki, Director of Engineering Department overseeing product design and Development, at Renesas, spoke at the Atrenta Technology Forum First inYokohama.  This is Tech-On’s coverage of his presentation and his evaluation of SpyGlass Physical, which is an EDA tool for estimating chip area and logic depth at the RTL stage:

http://www.nikkeibp.co.jp/article/news/20120720/316569/

 

 

 

 

Lee PR does work for Atrenta

 

Gary Smith on NextOp, now Springsoft

Tuesday, August 7th, 2012

Yesterday we heard from Jim Hogan on the NextOp acquisition.  Today Gary Smith chimes in on NextOp and the recent Springsoft buyout.

Ed:  What do the Atrenta acquisition of NextOp and the Synopsys acquisition of Springsoft mean to EDA?

Gary:  Technology wise the Atrenta acquisition means that the Silicon Virtual Prototype is becoming a reality.  Business wise it could be the start of the roll-up in the middle.

Springsoft was always a possible roller-upper but generally thought of as a long shot because of theirTaiwanheadquarters.  Springsoft certainly makes Synopsys stronger, especially with the Laker analog product, but doesn’t affect the SVP or the RTL sign-off tool market.  Debug is just being rolled up into the simulator.

Ed:  What sort of new day does it herald for EDA?

Gary:  With the creation of the SVP we now have the RTL sign-off established. This then is the breakpoint between design and implementation, just as the gate-level netlist was in the past.  This will free up a large group of designers, and enable a new larger group of designers, which in-turn will cause the explosion of new systems development.

Ed: What’s the significance?

Gary:  Growth, opportunity, money; the usual stuff.

 

 

 

 

Lee PR does work for Atrenta

 

 

 

Atrenta’s unified platform

Tuesday, May 15th, 2012

Maybe Atrenta is saying goodbye to the thought-bubble guy…..

Atrenta’s SpyGlass has always been the dominant name in the company’s brand portfolio,and for good reason. It’s the dominant product in RTL design analysis, verification and optimization.

Now, Atrenta is reconfiguring its product lineup to formalize this state of affairs. SpyGlass now becomes the unifying platform for all Atrenta products.  Sort of the mother ship that all Atrenta products are based on.

So what’s a unified platform? All the tools now share a common set up and debugging methodology and tighter GUI. And what can users verify and optimize from this new unified platform? Syntax, power, testability, clock synchronization, timing and routing congestion. All at the RTL stage, well before detailed implementation begins.

(more…)

3D in Monterey Next Week

Thursday, March 29th, 2012

 

This event is happening next week! Worth signing up if you can get down
there!………

 

EDPS is coming up again!  It’ll be held April 5-6, 2012 at the Monterey Beach Hotel in Monterey California.

This year, the 3D topic will be the focus of day two.

First and foremost,  Riko Radojcic, director of engineering at Qualcomm, will be talking about the 3D IC roadmap as the keynote speaker on day two.   (see his views on 3D standards:  http://www10.edacafe.com/blogs/ed-lee/2011/04/11/riko-radojcic-on-3d-standards/

Following the 1-hour keynote will be four 1/2 hour talks on various specific 3D-related topics:

* Stephen Pateras of Mentor on BIST for 3D ICs

* Arif Rahman of Altera on FPGA design challenges, presumably 3D ones

* Marc Greenberg of Cadence on the wide-IO standard for putting memory stacks on processors

* Sandeep Goel of TSMC and Bassilios Petrakis of Cadence on an end-to-end test flow for 3D IC stacks

Then there’s a lunch panel on 3D, moderated by Steve Leibson of Cadence,  with these panelists addressing: The short-, medium and long-term path to the 3D Ecosystem.

* Herb Reiter

* Samta Bansal of Cadence

* Dusan Petranovic of Mentor

* Deepak Sekar of Monolithic 3D

* Steve Smith of Synopsys

* Phil Marcoux of PPM Associates

Herb is arguably the primary 3D observer and advocate on what technologies have to be in place to handle the upcoming 3D challenge that’s starting to hit designers now.

John Swan is the General Chair of EDPS 2012. Herb Reiter is the Session Chair for the keynote, four shorter presentations and the panel discussion during  “3D Day”, Friday, April 6.

Very worthwhile to attend if you can get the time off.

3D in Monterey

Thursday, March 22nd, 2012

EDPS is coming up again!  It’ll be held April 5-6, 2012 at the Monterey Beach Hotel in Monterey California.

This year, the 3D topic will be the focus of day two.

First and foremost,  Riko Radojcic, director of engineering at Qualcomm, will be talking about the 3D IC roadmap as the keynote speaker on day two.   (see his views on 3D standards:  http://www10.edacafe.com/blogs/ed-lee/2011/04/11/riko-radojcic-on-3d-standards/

Following the 1-hour keynote will be four 1/2 hour talks on various specific 3D-related topics:

* Stephen Pateras of Mentor on BIST for 3D ICs

* Arif Rahman of Altera on FPGA design challenges, presumably 3D ones

* Marc Greenberg of Cadence on the wide-IO standard for putting memory stacks on processors

* Sandeep Goel of TSMC and Bassilios Petrakis of Cadence on an end-to-end test flow for 3D IC stacks

Then there’s a lunch panel on 3D, moderated by Steve Leibson of Cadence,  with these panelists addressing: The short-, medium and long-term path to the 3D Ecosystem.

* Herb Reiter

* Samta Bansal of Cadence

* Dusan Petranovic of Mentor

* Deepak Sekar of Monolithic 3D

* Steve Smith of Synopsys

* Phil Marcoux of PPM Associates

Herb is arguably the primary 3D observer and advocate on what technologies have to be in place to handle the upcoming 3D challenge that’s starting to hit designers now.

John Swan is the General Chair of EDPS 2012. Herb Reiter is the Session Chair for the keynote, four shorter presentations and the panel discussion during  “3D Day”, Friday, April 6.

Very worthwhile to attend if you can get the time off.

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