Before the summer ends and the summer blockbuster movies and DAC become a distant memory (still shaking my head over The Lone Ranger’s flop), let me just share Mike Gianfagna’s vision for next summer’s blockbuster.
It’s a tad more like Terminator 2 than the masked man and Tonto. And it may not be too far from reality – that’s what’s exciting…..and scary.
Of course it’s about the semiconductor supply chain and how it might affect our lives in the future.
Sage Design Automation, Inc. announced its founding technology last month and created a lot of customer and media buzz at DAC’13 inAustin. I bet a lot of people were surprised that design rule manual creation and DRC deck implementation were manual, error-prone tasks – especially as we get into smaller process geometries – and that they can take years to put one together.
In a way, it’s a lot like writing a long paper on a typewriter, or even by hand. When you make an error, you use White Out (remember that?) or type back over the error with the erasing ribbon. There’s no way to correlate the paper’s index, spell check, grammar check or check for consistency.
So we accosted Sage-DA president and CEO Coby Zelnik to ask him about this problem, one that many of us assumed just took care of itself! Here’s what he had to say.
With less than 3 weeks away until DAC’13, Liz and I asked Warren Savage about IPextreme’s and Constellations’ planned presence there. Warren is not only founder and CEO of IPextreme, but also head of the IP consortium, Constellations.
We caught up with Warren recently, and Mike Gianfagna, VP of Corporate Marketing at Atrenta (Atrenta is a Constellations partner), happened to be there. So, the two of them let us in on what Constellations would be up to at DAC.
Liz: Warren, what play does IP have at DAC this year?
Warren Savage President and CEO IPextreme
Warren: Change is slow, but IPextreme and Constellations are happy to report change is afoot and our workshop at DAC serves as a prime example of this. Together with TSMC and our Constellations partners Atrenta and Sonics, we are pleased to present “Driving Quality to the Desktop of the DAC Engineer” on Sunday, June 2 from 1:00 to 5:00 PM. This workshop showcases a foundry, two IP companies, and an EDA company working together—exactly as we do every day.
Why, then, is this the first DAC workshop of its kind? Why have the ties binding us together in the semiconductor ecosystem not been highlighted before? Perhaps the old saying, “If all you have is a hammer, everything looks like a nail,” is the only explanation. At the end of the day, our customers need all of us – both IP providers and EDA vendors. We owe it to them not only to recognize that, but also to make their lives easier by working together.
These two trend setters share their opinions on the BIG DACthemes in 2013.
I see two related trends:
1) More signoff activity earlier in the design flow
2) More focus on IP quality and usability
Both of these trends represent a maturing of design tools and business models. Because of the tremendous complexity that sub-20 nm design brings, it becomes more important to get the design right as early as possible. The tools are maturing in the earlier stages, and more designers are demanding clean reports, or sign-off level quality audits as a result. This is helping to reduce schedule delays and design costs – good for the industry.
Semiconductor IP is also maturing – both use models and business models. There is a growing focus on reporting delivered quality and robustness. This will allow IP providers that deliver the best IP to flourish. Also good for the industry. We’ll see an increase in conversations about IP providers collaborating with the rest of the ecosystem at DAC. Another good trend.
DAC is upon us….and in Austin, of all places – the island in the middle of Texas.
As it’s getting closer, we were wondering what the BIG theme is for the 50th DAC. So, we asked a few of our friends and colleagues in the industry. Here’s what a few of them had to say.
I expect DAC to continue to explore low power challenges, with much talk about solving FinFET issues at 14 and 10 nm. Then there is the ever expanding SoC and how to handle all of the challenges that come with greater integration and IP reuse. Finally, what’s DAC without a discussion of Moore’s Law and whether it will/won’t continue to define industry progress in the years to come?
In a casual conversational exchange I overheard last week at DVCon (which reminded me of what Steve Jobs said to John Scully – “Do you want to sell sugared water for the rest of your life or do you want to…change the world?” – someone asked if the other’s company wanted to dink out press releases forever or if the company wanted to tell a story that mattered to its audiences.
This conversation got me thinking……There’s nothing wrong with sending out press releases but companies get optimal effect and value when they issue press releases for more than mere information distribution.
What would that be? To reinforce, substantiate or bolster the company’s story. Sending out press releases (or saying, writing or doing any outbound efforts) ought to convey at least one of the company’s message points.
Our next prediction comes from respected blogger, consultant and software architect, algorithm, EDA and cloud computing expert, Olivier Coudert.
In 2013, one major semiconductor company will use the services of a third party to offload its computing resource requirements (for synthesis, simulation, signoff, shared project, or anything they deem important) to the cloud. This third party will work with EDA vendors and cloud providers to build virtual design centers, where customers are given the means to develop, test, and sign off their product. And when I say “cloud” I mean major players in the cloud computing market.
Some semiconductor companies have been feeling the pain of capital investment in datacenters they only need at peak hours. So those companies are getting smart and will work with third party companies to access virtual design centers, build on demand, and pay as-they-go.
Soon any startup will have access to the computing resources and the EDA software they need to focus on innovation without breaking the bank. A new model for hardware startups, which the VCs will love. You will no longer need $10M to fund a hardware company, just a few $100Ks.
Stale IP is beginning to rear its ugly head. It’s like having too many books on your bookshelf – always an issue in my house. Where do you put the new ones? Which ones do you keep? What do you do with the ones you don’t want to keep?
I (Liz Massingill) recently polled some experts in the industry to get their stance on stale IP. Over the next few weeks I’ll share their views with you.
I’ll start with Harrison Beasley, Manager of the Technical Working Groups at Global Semiconductor Alliance (GSA). Here’s what he had to say:
Liz: Stale IP – what is it?
Harrison: IP becomes stale when the underlying code is out of date. This could be due to changes in a specification, errors found in use, soft IP not being updated, etc. My assumption is that stale IP will not perform the task for which it was created.
Liz: What’s so bad about it?
Harrison: Using stale IP could lead to non-functional silicon, tape out delays, end product failures, etc.
Liz: How do we prevent it from being stale?
Harrison: For internal IP, code checks before layout, during timing analysis, during verification, and before final tape-out help ensure the latest IP version is used. For third party IP, similar rules apply, but the user must coordinate with the IP Supplier to ensure changes are promulgated to the user.