Narayana Koduri’s article on Power Awareness in RTL Design Analysis was the second of two Atrenta articles that EE Times editor Brian Bailey named as the ten most-read contributed articles published in EDA Designline. Along with number one article Understanding Clock Domain Issues by Saurabh Verma and Ashima Dabare, Atrenta appears to be the only company with two articles in this top ten list.
So even though his article appeared in July 2012, we asked Narayana to give us an update on what he sees as the power awareness challenges. Here’s what he had to say.
Ed: Narayana, your article sure addressed a hot topic in SoC design. And judging by the readers you got, the design community liked what you had to say. What can you add to your July 2012 article?
Narayana: Thanks Ed. From what I can see, due to aggressive low power requirements, power domains are being implemented in a growing number of SoC designs to reduce both leakage and dynamic power.
Ed: How so?
Narayana: UPF or CPF can be used to define the power intent to capture information such as power domains, level shifter requirements, isolation cells, retention cells, power switch cells, etc. These specifications will help implementation tools and verification tools to deal with the power intent properly.
Ed: So how best to deal with power intent?
Narayana: RTL tools that verify aspects of the SoC such as clock domain crossings, testability, timing and routing congestion need to be aware of the power intent. If not, the verification is not complete and this may lead to design failures or a costly re-spin of the design. This need for power-aware verification is driving new requirements in the EDA tool flow.
NOTE: For an update on Understanding Clock Domain Issues see our blog of October 3.
Note: Lee PR does work for Atrenta