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Posts Tagged ‘Brian Bailey’

What is the EDA Editorial Brain Trust Today?

Monday, August 25th, 2014

 

The EDA editorial brain trust today is the topic of our continuing conversation with Richard Goering and Brian Fuller.  

 

Brian Fuller

Brian Fuller

Richard Goering

Richard Goering

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ED:  What is the EDA editorial brain trust these days?

RICHARD: Not sure how you’re defining “brain trust,” but if there is one, it’s with the vendors and the independent on-line publications.

ED:  Who makes up the EDA editorial brain trust?

RICHARD:  If you add it all up, there are still a number of editors with deep EDA and semiconductor experience – they’re just no longer with print publications.

Additionally, there are now a number of writers and bloggers who didn’t start as journalists but who turned in that direction during the transition away from print.

(more…)

Predictions 2014: Brian Bailey on a new opportunity for EDA

Sunday, February 9th, 2014

 

Next up is Brian Bailey, Technology Editor/EDA, for Semiconductor Engineering, who has shared his forecast for EDA in 2014. 

“Over the next couple of years there will be an increase in ASIC starts, but not all of these will be for the latest technology nodes or be the massive chips we have come to expect. The new starts will be smaller chips that form the leaves of the Internet of Things, things such as sensors with small amounts of processing and communications. They will be targeting older processes, such as 90nm. Margins on these devices will be slim but volumes high. I see the designers of these products requiring a different mix of capabilities in their EDA tools and different price points. It may create an interesting opportunity for the second tier EDA companies to become significantly bigger.”

The Internet of Things

Sunday, June 16th, 2013

 

As Mike Demler predicted back in May, the “Internet of Things” was all the buzz at DAC this year. 

Freescale CEO Gregg Lowe talked about the opportunities and challenges in his keynote.  

Mentor CEO Wally Rhines said in his keynote that the big growth in the semiconductor industry will come with the Internet of Things. 

It was simultaneously discussed at the GSA European Executive Forum in Munich and the Sensors Expo in Chicago

What do you think? 

Is it the next big thing? 

Can EDA step up to the challenge? 

And what does it mean to our future?

On Power Awareness in RTL design analysis: Update to a Brian Bailey-designated Top Ten Atrenta article

Wednesday, October 10th, 2012

 

Narayana Koduri’s article on Power Awareness in RTL Design Analysis was the second of two Atrenta articles that EE Times editor Brian Bailey named as the ten most-read contributed articles published in EDA Designline.    Along with number one article Understanding Clock Domain Issues  by Saurabh Verma and Ashima Dabare, Atrenta appears to be the only company with two articles in this top ten list.

So even though his article appeared in July 2012, we asked Narayana to give us an update on what he sees as the power awareness challenges.  Here’s what he had to say.

Ed:  Narayana,   your article sure addressed a hot topic in SoC design. And judging by the readers you got, the design community liked what you had to say.  What can you add to your July 2012 article?

Narayana:  Thanks Ed.   From what I can see, due to aggressive low power requirements, power domains are being implemented in a growing number of SoC designs to reduce both leakage and dynamic power.

Ed:  How so?

Narayana:  UPF or CPF can be used to define the power intent to capture information such as power domains, level shifter requirements, isolation cells, retention cells, power switch cells, etc. These specifications will help implementation tools and verification tools to deal with the power intent properly.

Ed:  So how best to deal with power intent?

Narayana:   RTL tools that verify aspects of the SoC such as clock domain crossings, testability, timing and routing congestion need to be aware of the power intent. If not, the verification is not complete and this may lead to design failures or a costly re-spin of the design. This need for power-aware verification is driving new requirements in the EDA tool flow.

NOTE:  For an update on Understanding Clock Domain Issues see our blog of October 3.

 

 

 

 

Note:  Lee PR does work for Atrenta

 

ICScape got $28M funding, exhibits for first time at DAC

Friday, May 25th, 2012

 

Named by industry observers as “the biggest EDA company you’ve never heard of” and “a rare and endangered species” of EDA companies, ICScape will bolt out of stealth mode to exhibit at DAC for the first time.

Founded in 2005 by Steve Yang and Jason Xing, the company’s been busy over the last year.  How?  Merging with analog EDA vendor Huada Empyrean Software (HES), getting that US$28M infusion to fund global R&D, customer support and sales expansion, and working on OpenAccess-based product lines that we’ll probably see in some integrated form toward the end of 2012.

ICScape’s booth will greet attendees right at the entrance to the exhibit floor, in Booth 1602.   The company’s executives will be there to:

1)  talk about its technology,

2)  introduce current customers (a major silicon valley Fabless IC company and a major Silicon Valley analog device company) who will also be available at the booth to share firsthand experience,…..and

3)  ensure that ICScape will be one of the EDA names that all of you will have heard of.

See what Paul McLellan,  Mike Demler and  Brian Bailey have to say about ICScape:

http://www.semiwiki.com/forum/content/1248-biggest-eda-company-you-ve-never-heard.html

http://www.eedailynews.com/2012/05/examining-rare-and-endangered-species.html

http://www.eetimes.com/electronics-blogs/other/4372423/New-Companies-exhibiting-at-DAC—ICScape

See you at DAC!

 

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Note:  Lee PR does work for ICScape.

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