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Posts Tagged ‘board-level analysis’

AtaiTec co-author shows how reducing skew can improve a channel’s insertion-loss-to-crosstalk-ratio

Wednesday, October 8th, 2014

AtaiTec Corp. president Dr. Ching-Chao Huang co-authored a DesignCon 2014 paper that looks at new methodologies to characterize connectors for 25+ Gbps boards.

What’s eye opening is how the authors used AtaiTec’s In-Situ De-embedding (ISD) software to extract connector-only data from a large board and compare them directly with simulation results from a 3D field solver.

Learn more about this finding here:



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