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Posts Tagged ‘Bernard Murphy’

Jim Hogan and Bernard Murphy on IoT Security: How the human body’s defense mechanism may be the model for repelling attacks on the IoT

Thursday, October 16th, 2014


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This article by Atrenta’s CTO Bernard Murphy and investor Jim Hogan has attracted a lot of interest.

Murphy and Hogan say that we can draw inspiration from biology on how to design the IoT fortress: specifically, how the human body wards off attacks from bacteria, viruses, other bad and harmful stuff.

And they describe in detail the concept on how electronic engineers can plan to do so.

It’s an intriguing piece  that gives electronic designers a first huge step on how to secure the IoT and keep those of us who are IoT-interconnected – Borg Collective like – protected from the inevitable cyber attacks.

Biology, Deceit & Security in the Internet of Things

What do you think?


The Internet of Everything – What are we really facing?

Monday, July 21st, 2014


As we had previously announced, venture capitalist Jim Hogan moderated a panel at DAC regarding the IoT. 

_MG_7133-no-halo (2)_mediumIt was an eye opener about all things IoT……or maybe we should call it the IoE (The Internet of Everything), or as one prominent editor noted, the IoW (The Internet of Whatever).  Our panelists included:  Gary Smith, Market Analyst, GSEDA; Frank Schirrmeister, Group Director, System Development Suite, Cadence; Bernard Murphy, CTO, Atrenta; and Randy Smith, VP of Marketing, Sonics.

Very lively discussion among panelists, but also from the floor!  Most notably editor Gabe Moretti of Chip Design and Simon Bloch of Samsung.  Bloch, Sr. Director of R&D in mobile consumer wireless devices, posed questions and stimulated discussion to the point where he might be called the unannounced 6th panelist.

Over the next few blogposts, we’ll share snippets of that discussion.  Gary Smith will start us off…..


What is the IoT?…Jim Hogan convenes discussion at DAC

Tuesday, May 20th, 2014

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As DAC frenzy hits us all, here’s an event that EDA/IP users and media people ought to consider attending.


It’s a Jim Hogan-moderated discussion event on

IoT system design concerns

Jim will 1) introduce the topic; 2) spur, moderate, provoke discussion and 3)  sum up what we’ve learned during this session.  Of course, this group of speakers are pretty opinionated and won’t need much provocation.


Finding Love at DAC… Atrenta

Sunday, June 19th, 2011

You saw the trailer……



Are you curious what happened next….whether this young man found love… DAC?  In case, you missed it – here’s the rest of the story……


BTW the CTO of the SoC Realization Company expresses his views on the future of the technology and business of EDA and what’s needed in EDA tools in this video on System-Level Design…..



Full Disclosure: Lee PR works for Atrenta.


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Chip Killers: keeping design managers awake

Monday, February 7th, 2011

Am I gonna make tapeout in time?Liz and I attended a panel at DesignCon that asked the question: what are you doing about the chip killers that delay your tapeout? That’s an intriguing, possibly unanswerable thought, since we’ve asked that question virtually since EDA’s inception. Ed Sperling of Systems-Level Design moderated the panel which had on it: Sunil Malkani of Broadcom, Ravi Damaraju of Juniper, Ramon Macias of NetLogic, John Busco of NVIDIA and Bernard Murphy of Atrenta.

Sperling moderated a lively discussion; questions that he or the panelists or audience posed highlighted the ongoing nature, or unanswerability of the topic. Some were:

• As designers and design managers, what keeps you up at night?

• If your design has to finish in half the time that your previous project took, do you start with a [design methodology and flow] clean slate?

• How do you get hardware and software engineers to work together?

• What’s good enough to get the design out the door?

• How do you define failure?

• What’s the price of failure?

• Who owns quality?

• What do you do when your next project is 4X the size of your last design? Throw people at it? Make the tools do more? Run faster? How?

• How do I turn around a design in a month and get all of these [now-required] apps on it?

• Why does place & route have to be flat?

• When will P&R, timing analysis have to break down the design hierarchically?

• How can verification be improved so that its pessimistic estimates won’t require designers to over-design?

The panelists all bemoaned the dueling standards that plague EDA, attributing them to companies wanting to gain marketing advantage, to the detriment of EDA users.

Sperling will publish a transcript of this panel in a future issue of System-Level Design. Nic Mokhoff published a summary of the panel the next day.

Finally, I have a question: why does DesignCon schedule a management-level panel on a day when the exhibit floor isn’t open? Doesn’t help DesignCon panels’ attendance, which has been paltry for years, seems to me.

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