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Posts Tagged ‘3D’

Predictions 2014: Sumit DasGupta on ensuring a vibrant semiconductor industry

Wednesday, February 26th, 2014

Retired senior vice president of Si2, Sumit DasGupta, imparts his sage view on what the semiconductor, EDA and IP industries should focus on to ensure a vibrant semiconductor industry for 2014. 

“As the new year rolls out, there are promises and associated challenges that the semiconductor industry faces that need attention to ensure the vibrancy of the industry, even as the industry struggles to stay on the Moore’s law trajectory.

First in my list is the area of 2.5D and 3D integration, an area of great promise but with significant challenges. Much has been touted about these approaches as ways to deliver “More than Moore” but it appears to this observer to be advancing at a pace that is slower than hoped for. It seems to be just another year away from full production. But now, enough said, 2014 needs to be the year when much greater focus must be applied to get at least 2.5D technology into mass production. This is not a transitory approach to 3D but rather should last longer in its own right as a very viable technology sitting alongside 3D as 2 approaches to semiconductor integration. 3D still has challenges to be addressed but here again, greater focus needs to be applied to ramp up to full production in 2015.

(more…)

3D in Monterey Next Week

Thursday, March 29th, 2012

 

This event is happening next week! Worth signing up if you can get down
there!………

 

EDPS is coming up again!  It’ll be held April 5-6, 2012 at the Monterey Beach Hotel in Monterey California.

This year, the 3D topic will be the focus of day two.

First and foremost,  Riko Radojcic, director of engineering at Qualcomm, will be talking about the 3D IC roadmap as the keynote speaker on day two.   (see his views on 3D standards:  http://www10.edacafe.com/blogs/ed-lee/2011/04/11/riko-radojcic-on-3d-standards/

Following the 1-hour keynote will be four 1/2 hour talks on various specific 3D-related topics:

* Stephen Pateras of Mentor on BIST for 3D ICs

* Arif Rahman of Altera on FPGA design challenges, presumably 3D ones

* Marc Greenberg of Cadence on the wide-IO standard for putting memory stacks on processors

* Sandeep Goel of TSMC and Bassilios Petrakis of Cadence on an end-to-end test flow for 3D IC stacks

Then there’s a lunch panel on 3D, moderated by Steve Leibson of Cadence,  with these panelists addressing: The short-, medium and long-term path to the 3D Ecosystem.

* Herb Reiter

* Samta Bansal of Cadence

* Dusan Petranovic of Mentor

* Deepak Sekar of Monolithic 3D

* Steve Smith of Synopsys

* Phil Marcoux of PPM Associates

Herb is arguably the primary 3D observer and advocate on what technologies have to be in place to handle the upcoming 3D challenge that’s starting to hit designers now.

John Swan is the General Chair of EDPS 2012. Herb Reiter is the Session Chair for the keynote, four shorter presentations and the panel discussion during  “3D Day”, Friday, April 6.

Very worthwhile to attend if you can get the time off.

3D in Monterey

Thursday, March 22nd, 2012

EDPS is coming up again!  It’ll be held April 5-6, 2012 at the Monterey Beach Hotel in Monterey California.

This year, the 3D topic will be the focus of day two.

First and foremost,  Riko Radojcic, director of engineering at Qualcomm, will be talking about the 3D IC roadmap as the keynote speaker on day two.   (see his views on 3D standards:  http://www10.edacafe.com/blogs/ed-lee/2011/04/11/riko-radojcic-on-3d-standards/

Following the 1-hour keynote will be four 1/2 hour talks on various specific 3D-related topics:

* Stephen Pateras of Mentor on BIST for 3D ICs

* Arif Rahman of Altera on FPGA design challenges, presumably 3D ones

* Marc Greenberg of Cadence on the wide-IO standard for putting memory stacks on processors

* Sandeep Goel of TSMC and Bassilios Petrakis of Cadence on an end-to-end test flow for 3D IC stacks

Then there’s a lunch panel on 3D, moderated by Steve Leibson of Cadence,  with these panelists addressing: The short-, medium and long-term path to the 3D Ecosystem.

* Herb Reiter

* Samta Bansal of Cadence

* Dusan Petranovic of Mentor

* Deepak Sekar of Monolithic 3D

* Steve Smith of Synopsys

* Phil Marcoux of PPM Associates

Herb is arguably the primary 3D observer and advocate on what technologies have to be in place to handle the upcoming 3D challenge that’s starting to hit designers now.

John Swan is the General Chair of EDPS 2012. Herb Reiter is the Session Chair for the keynote, four shorter presentations and the panel discussion during  “3D Day”, Friday, April 6.

Very worthwhile to attend if you can get the time off.

Predictions 2012 – Persistence of Memory

Thursday, February 9th, 2012

To finish off our series of predictions, I would like to point you to another series of interesting and informative prophesies.  Click on the following topics to see these predictions collected by Brian Bailey, Editor of EDA DesignLine.

Industry Trends

Tools

ESL

IP and Physical Design

The Bold Prediction for EDA

 

A big THANK YOU from Ed & me (Liz) to all who shared their eye opening predictions with us.  Click on their names to see their predictions.  Mike Gianfagna, Karen Bartleson, Paul McLellan, Jens Andersen, Bob Smith, Steve Schulz, Mathias Silvant, Herb Reiter, Max Maxfield, Chris Edwards, John Barr.

 

Only time will tell……

 

The Persistence of Memory, 1931, Salvador Dali

 

Predictions 2012 – 2.5D

Tuesday, January 24th, 2012

A number of 2.5D IC designs will hit the market and demonstrate both the value of 2.5/3D technology as well as the importance of powerful and user-friendly tools for “Pathfinding”, to quickly identify the best (lowest cost) implementation alternative.

Herb Reiter
President
eda 2 asic Consulting, Inc.
www.eda2asic.com

 

Predictions 2012 – 3D a-coming

Thursday, January 19th, 2012

Industry pressure is growing to deliver more mainstream 2.5D and 3D stacked die semiconductor products within the next 1-2 years, driven by the need to improve I/O bandwidth, reduce power consumption, and optimized choice of process technologies for different portions of a complex SoC.  It is therefore quite possible that 2012 will see one of the large mainline EDA vendors broadly announce a full “platform” product suite targeting the design of 2.5D and 3D stacked die making use of through-silicon-vias (TSV’s).  This design platform would likely incorporate tools from value-added niche vendors, and be endorsed in a large foundry reference flow.  Open standards will later expand the range of choice and interoperability over time.

Steve Schulz
President and CEO
Si2
www.si2.org

 

Predictions 2012 – Mergers and 3D

Wednesday, January 11th, 2012

And the predictions begin……

 

With regard to “Events” – 2012 will be a year of further acquisition and consolidation for both the EDA and IP industries.  Some new faces will join the dance, with significant resources at their disposal. It is likely the “Big 3″ will have at least one new name in a year’s time.

With regard to “Breakthroughs” – it’s a different story.  3D stacked-die design still won’t be mainstream in a year’s time.  True hardware/software co-design will still be a developmental area and verification will still be as hard as ever.  Many panels, blogs, seminars and special conference sessions will debate these topics throughout the year with great hope and excitement, however.

Mike Gianfagna
Vice President of Marketing
Atrenta Inc.

http://www.atrenta.com/


 

 

Will it be the end of the world or just shrinking EDA? Mystics Muse about Money, Mergers and Multiple SoCs

Tuesday, January 10th, 2012

 

Step aside Nostradamus and Mayans.  The real earth-shattering events of 2012 could take place in the EDA & IP industries.  We asked industry friends, associates, clients and media folks to ponder what industry-shattering events or breakthroughs we might see in EDA & IP this coming year.

So what topics came up?  Consolidation of the industry; standards; various technologies, 3D being the most discussed; even one man’s blatant personal goal.  :-)

We heard the word “challenge” a lot, for the big vendors and the smaller companies.  So will two foundry-led EDA mega-companies duke it out with a third mega-company, as one diviner foretold?   Tough to tell how tongue-in-cheek his prophesy was.

So we’ll post the visionary comments of one individual at a time, in the order they came into us.  We found them enlightening and even entertaining!  We hope you do too.

 

Liz and Ed

 

Riko Radojcic on 3D standards

Monday, April 11th, 2011

Liz and I sat down with Riko Radojcic of Qualcomm to hear his thoughts on how upcoming 3D design and manufacturing would affect the EDA world.    Naturally, the conversation morphed into a discussion about standards that will be required to make 3D adoption pervasive.

Liz: Thanks for taking the time out of your busy schedule to sit down with us, Riko. So let me ask you, what is the relevance or importance of standards in adopting 3D?

Riko: Well, first, let me make a general statement about standards.  Sometimes some of the EDA companies view proprietary formats as a source of competitive advantage – a way of locking in a customer base.  This is especially true when a given company has taken a lead with a given solution, and they fear that opening up a proprietary format would shrink their slice of the market pie. However, in general, design standards, or standard exchange formats, or standard models, tend to make the whole pie bigger, as opposed to affecting the size of any one’s slice of the pie. So, in the long run, standards are good for users, like Qualcomm, and for vendors, like the EDA companies.  I keep referring back to the industry experience with SPICE models and the transition from the proprietary ‘Level 28’ model to the open standard BSim generation of models.  I think with all the brilliance of hindsight, the industry has benefited from an open standard model.

For 3D technology specifically, we are promoting the concept of standards, in order to accelerate the adoption of 3D design and manufacturing methods.  We want to help to line up the supply chain behind the 3D technology. I would say that most people – users, industry observers, EDA vendors, etc. all perceive 3D technology as a disruptive change.  The fear of that change is part of the barrier to adoption.  Standards are the other side of this coin of fear.  They bring down the feeling of fear.

Ed: Is 3D more a barrier to standards?  Are we sabotaging our own efforts?

Riko: There is a lot of FUD in 3D.  It is important to realize that there is 3D and then there is 3D.  Some future 3D implementations – like stacking logic on logic – does require disruptive change in design tools.  We will need design methodologies and tools that comprehend entirely a new dimension of parameters for this class of designs, and until these are developed, standards may even be a bit of a barrier.

On the other hand, 3D in the short term means heterogeneous stacking, like memory on top of logic.  So right now, 3D is not that disruptive.   We only need some minor upgrades to design logic in a smart way, to make stacking DRAM on top of it easier and lower risk. For this class of designs, standards would be extremely helpful – having a standard exchange format so that we have relevant information about die A when designing die B or vice versa would be excellent.  For example designing power distribution network on die A needs to know about power demands on die B.

To accelerate and facilitate adoption, we need more design information.   JEDEC for example is doing a nice job of working on the standards for memories

Liz: What is JEDEC doing?

JEDEC is defining the pin assignment and the pin array configuration required for Wide IO DRAM memories to be stacked on logic die.

Ed: What of vendors’ fears that buying into this format will be giving away too much of their own design data?

Riko: We can all make an investment in a standard format that can provide the right characteristics without exposing too much information.  The emphasis is on format, rather than specific content – which should be proprietary.  Again I like to refer back to SPICE and BSim models – where the model format, units, etc. are standardized, but the specific coefficients in the model are proprietary information of whoever owns the process technology.

Liz: Why is this not happening now?

Riko: We are all driven by financial motives.  No one feels they will make enough money out of it right now – and this is especially true for standards, which, by definition, belong to everybody. However, there could be certain advantages for someone creating a standard and then giving it away.  If you make the rules, you have a better chance of winning the game.

The thing that is required is a series of standard ‘exchange formats’ that would communicate the necessary information about the design of the various die to be stacked,  such that 3D stacking of these die is a low risk enterprise.  Basically to communicate design attributes such as power demand characteristics, thermal and mechanical stress sensitivities, maybe some floorplanning restrictions, etc..

Most of the standards bodies don’t have the capability to develop such standards. They have mechanisms to review a proposed standard and to manage and distribute it afterwards – but not to do the engineering required to develop one.  So, there’s a lack of champions willing to put in the work to develop and promote a standard.  It could be an EDA company, like Apache, or it could be an institution, like IMEC, or it could be an academic entity.

There are some activities going on, though. IMEC is working with Atrenta to develop a PathFinding tool – which may also involve developing a PathFinding exchange format.  Apache has taken the lead in pushing a standard power exchange format for 3D. Perhaps some of the academics could be engaged to develop standard exchange format proposals?  Si2 is willing to take a role in managing the standards, but someone needs to give them something to standardize.  GSA is active and willing to coordinate the discussions. But someone needs to make a proposal so the industry can say “I like it” or “I don’t like it” or whatever.

Liz: So you are looking for another EDA guy to come up to the plate, and then what if someone like Cadence comes up with a competing idea?  Then what?

Riko: Once a product is developed, all the EDA companies are invested in one format or another.  We want to get these standards in front of the product development curve, so that it would be easier for any one company to adopt and comply with a standard, rather than  making up their own format.  This is where the users – such as Qualcomm – come in.  We have the responsibility to demand this.

Ed: So it sounds like so far, we have a lot of discussion, but to a certain extent, some organizations are waiting for others to discuss or define a proposed set of 3D standards.   Other organizations are waiting for that proposal to get adopted before implementing the 3D standards.   How do we get off this merry-go-round?

Riko: I would say, let’s take a stab at partitioning the effort.  Qualcomm proposed this last September, at a SEMI/Sematech sponsored meeting in Taiwan.   We proposed dividing the world into two buckets…one set of players and activities focused on design related standards,  and another for manufacturing related standards. For each bucket of standard related activities, we proposed a suitable existing standards body, a suitable forum for discussion, and a suitable set of champions who would propose appropriate standards.  In the manufacturing domain, it would make sense to use SEMI to manage the standards, and Sematech to provide the Proposals. In the design domain it would make sense to use Si2 to manage the standards, and EDA or academics that are involved with EDA to provide the proposals. That way there would be less overlap and hopefully fewer gaps

Liz: What would happen then?

Riko: In addition, we proposed to create a forum which would be conducive to exploring and kicking around some of the proposed standards.  Standards bodies, by definition have a formal review and balloting mechanism – which tends to be slow.  So, in order to accelerate the discussion a separate forum would be nice.  The Sematech 3D Enablement Center is doing this already for manufacturing-oriented standards.  Let’s work with GSA to create a forum to discuss design-oriented standards, and if (or when) a given proposal is flushed out, give it to Si2 to create a true standard.

Liz: Your 2011 hope or wish for 3D standards?

Riko: That our industry can actually define a standard without having to fight a turf war.   We can do this if we get ahead of the 3D product curve.  But only if we all pitch in.. .

Riko Radojcic, who has over 25 years in the semiconductor industry, is a Director of Engineering at Qualcomm, currently leading the Design-for-Through Silicon Stacking Initiatives.

 

 

 

Yet another 2010 EDA Trends write up?

Monday, January 18th, 2010

2009 was a rough year for an already stagnant EDA world. Looking to 2010, Liz Massingill and I asked industry colleagues, opinion makers and friends what each of them saw as the BIG trend for 2010.

Here’s what they said.

Karen Bartleson, Blogger, The Standards Game, Synopsys
http://synopsysoc.org/thestandardsgame/

The big trend in EDA for 2010 will be the acceptance of social media as an additional means for communicating with customers, partners, and competitors.

Now that blogging is settling in as a viable source of information from media people, company experts, and independent publishers, more new media tools will come into play. Not all tools are right for everyone or every situation, so the EDA industry will explore the options and experiment with a variety of community-development activities.

LinkedIn and Facebook will offer special interest groups a place to congregate. Twitter will be tested by more people – who today are curious or skeptical – as a means of immediate, brief interaction. EDA suppliers will offer new communication channels and those that are truly value-add will thrive.

The EDA world won’t change overnight, but the trends in social media will be noticeable.

Graham Bell, Director of Sales and Marketing, EDACafe
http://www10.edacafe.com/blogs/grahambell/

The BIG trend will be that designers need ALL of the technology that EDA companies have been working on and introduced in the last 18 months.

There is a lot of design work being done at 45nm and all the established tools are running at the edge of their capabilities.

New generations of parasitic extraction, static and statistical timing analysis, and automated property verification are just some of the important technologies that will be needed by design teams.

Mike Gianfagna, Vice President, Marketing, Atrenta, Inc.
http://www.atrenta.com

In 2010, we’ll see an accelerated move to doing more design at higher levels of abstraction.

Chip complexity and the skyrocketing cost of physical design, along with the advent of 3D stacks is forcing this. Designers just won’t be able to iterate in the back end in 2010 and beyond. It’ll take too long and cost too much.

Power management, design verification, design for test and timing closure will all be “close to done” before handoff to synthesis and place & route. The traditional backend flow of IC design will become a more predictable, routine process, which will accelerate its trend toward commoditization and consolidation.

This move to higher levels of abstraction will also have implications for IP selection and chip assembly. This will compel a new genre of tools to emerge. Standards like IP-XACT will help this process to take hold. Perhaps this is what ESL will become.

Richard Goering, longtime EDA editor and currently manager of the Cadence Industry Insights blog
http://www.cadence.com/Community/blogs/ii

I think the Big EDA Trend for 2010 will be SoC integration.

There will be a renewed focus on the challenges of integrating existing IP, providing breakthrough technology for design teams to quickly and reliably
assemble complex SoCs from integration-ready IP blocks, and then run
full-chip verification including both analog and digital components.

ESL is part of this story because there’s a need to move to
transaction-level IP creation, verification and integration. Hardware/ software integration and verification and will also become part of
the drive towards SoC integration.

Harry Gries, the ASIC Guy, EDA blogger
http://theasicguy.com/

As for the EDA trend in 2010, I think that EDA companies, when they recover, will choose not to hire more sales and marketing people but will invest more in other marketing tools on the Web or using social networking strategies.

A good example is a company like Xuropa, which is actually a client of mine, under full disclosure. They help EDA companies put their tools on the Web in order to help them reduce their costs for demos, product evaluations, etc.

I think that will see a lot of interest in the upcoming year as companies look for ways to do “more with less”. User group events may also move online, just like this year’s CDNLive was a virtual event rather than a real live event. Xilinx and Avnet sponsored an X-Fest this year that was also an online event. Things are moving online fast and economics will drive that.

Grant Martin, EDA blogger
http://www.chipdesignmag.com/martins/

In 2010, we’ll see the steady progress towards usable ESL tool and methodology adoption by design groups.

The areas of greatest real ESL use are the high level synthesis of data crunching blocks used in various DSP-type applications (signal and media processing), the increasing adoption of processor/SW-centric design methods, and the increased creation and use of virtual prototype models.

(Brian Bailey and I have a new book from Springer coming out in the new year on practical ESL use methods: “ESL Models and their Application: Electronic System Level Design and Verification in Practice”. See for a summary. )

Dan Nenni, EDA blogger
http://danielnenni.com/

For EDA, 2010 will be the year of the foundry. Foundries will drive new EDA flows and business models.

The TSMC Open Initiative Platform
is but the tip of the iceberg. If EDA and IP companies do NOT join forces with the foundries and take arms against the sea of semiconductor troubles – they will continue to suffer the slings and arrows of outrageous economic misfortune.

Coby Zelnik, CEO, Sagantec North America, Inc.
http://www.sagantec.com

In 2010, we will see more designs taping out in 40nm.

In an effort to minimize risk, cost and time to market, design reuse will be
maximized; many of them will be migrations of existing 90nm and 65nm products or derivative products with minor updates and tweaks.

– end –

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