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Posts Tagged ‘3D IC’

Predictions 2014: Sumit DasGupta on ensuring a vibrant semiconductor industry

Wednesday, February 26th, 2014

Retired senior vice president of Si2, Sumit DasGupta, imparts his sage view on what the semiconductor, EDA and IP industries should focus on to ensure a vibrant semiconductor industry for 2014. 

“As the new year rolls out, there are promises and associated challenges that the semiconductor industry faces that need attention to ensure the vibrancy of the industry, even as the industry struggles to stay on the Moore’s law trajectory.

First in my list is the area of 2.5D and 3D integration, an area of great promise but with significant challenges. Much has been touted about these approaches as ways to deliver “More than Moore” but it appears to this observer to be advancing at a pace that is slower than hoped for. It seems to be just another year away from full production. But now, enough said, 2014 needs to be the year when much greater focus must be applied to get at least 2.5D technology into mass production. This is not a transitory approach to 3D but rather should last longer in its own right as a very viable technology sitting alongside 3D as 2 approaches to semiconductor integration. 3D still has challenges to be addressed but here again, greater focus needs to be applied to ramp up to full production in 2015.

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Atrenta’s unified platform

Tuesday, May 15th, 2012

Maybe Atrenta is saying goodbye to the thought-bubble guy…..

Atrenta’s SpyGlass has always been the dominant name in the company’s brand portfolio,and for good reason. It’s the dominant product in RTL design analysis, verification and optimization.

Now, Atrenta is reconfiguring its product lineup to formalize this state of affairs. SpyGlass now becomes the unifying platform for all Atrenta products.  Sort of the mother ship that all Atrenta products are based on.

So what’s a unified platform? All the tools now share a common set up and debugging methodology and tighter GUI. And what can users verify and optimize from this new unified platform? Syntax, power, testability, clock synchronization, timing and routing congestion. All at the RTL stage, well before detailed implementation begins.

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3D in Monterey Next Week

Thursday, March 29th, 2012

 

This event is happening next week! Worth signing up if you can get down
there!………

 

EDPS is coming up again!  It’ll be held April 5-6, 2012 at the Monterey Beach Hotel in Monterey California.

This year, the 3D topic will be the focus of day two.

First and foremost,  Riko Radojcic, director of engineering at Qualcomm, will be talking about the 3D IC roadmap as the keynote speaker on day two.   (see his views on 3D standards:  http://www10.edacafe.com/blogs/ed-lee/2011/04/11/riko-radojcic-on-3d-standards/

Following the 1-hour keynote will be four 1/2 hour talks on various specific 3D-related topics:

* Stephen Pateras of Mentor on BIST for 3D ICs

* Arif Rahman of Altera on FPGA design challenges, presumably 3D ones

* Marc Greenberg of Cadence on the wide-IO standard for putting memory stacks on processors

* Sandeep Goel of TSMC and Bassilios Petrakis of Cadence on an end-to-end test flow for 3D IC stacks

Then there’s a lunch panel on 3D, moderated by Steve Leibson of Cadence,  with these panelists addressing: The short-, medium and long-term path to the 3D Ecosystem.

* Herb Reiter

* Samta Bansal of Cadence

* Dusan Petranovic of Mentor

* Deepak Sekar of Monolithic 3D

* Steve Smith of Synopsys

* Phil Marcoux of PPM Associates

Herb is arguably the primary 3D observer and advocate on what technologies have to be in place to handle the upcoming 3D challenge that’s starting to hit designers now.

John Swan is the General Chair of EDPS 2012. Herb Reiter is the Session Chair for the keynote, four shorter presentations and the panel discussion during  “3D Day”, Friday, April 6.

Very worthwhile to attend if you can get the time off.

3D in Monterey

Thursday, March 22nd, 2012

EDPS is coming up again!  It’ll be held April 5-6, 2012 at the Monterey Beach Hotel in Monterey California.

This year, the 3D topic will be the focus of day two.

First and foremost,  Riko Radojcic, director of engineering at Qualcomm, will be talking about the 3D IC roadmap as the keynote speaker on day two.   (see his views on 3D standards:  http://www10.edacafe.com/blogs/ed-lee/2011/04/11/riko-radojcic-on-3d-standards/

Following the 1-hour keynote will be four 1/2 hour talks on various specific 3D-related topics:

* Stephen Pateras of Mentor on BIST for 3D ICs

* Arif Rahman of Altera on FPGA design challenges, presumably 3D ones

* Marc Greenberg of Cadence on the wide-IO standard for putting memory stacks on processors

* Sandeep Goel of TSMC and Bassilios Petrakis of Cadence on an end-to-end test flow for 3D IC stacks

Then there’s a lunch panel on 3D, moderated by Steve Leibson of Cadence,  with these panelists addressing: The short-, medium and long-term path to the 3D Ecosystem.

* Herb Reiter

* Samta Bansal of Cadence

* Dusan Petranovic of Mentor

* Deepak Sekar of Monolithic 3D

* Steve Smith of Synopsys

* Phil Marcoux of PPM Associates

Herb is arguably the primary 3D observer and advocate on what technologies have to be in place to handle the upcoming 3D challenge that’s starting to hit designers now.

John Swan is the General Chair of EDPS 2012. Herb Reiter is the Session Chair for the keynote, four shorter presentations and the panel discussion during  “3D Day”, Friday, April 6.

Very worthwhile to attend if you can get the time off.

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