Ed LeeEd Lee has been around EDA since before it was called EDA. He cut his teeth doing Public Relations with Valid, Cadence, Mentor, ECAD, VLSI, AMI and a host of others. And he has introduced more than three dozen EDA startups, ranging from the first commercial IP company to the latest statistical timing analysis characterization company. Ed brings his knowledge of the history of the industry, the companies, the executives, the products, the editors, the analysts, the market researchers, and the investors. And crucially, he knows the trends and issues. « Less
Ed LeeEd Lee has been around EDA since before it was called EDA. He cut his teeth doing Public Relations with Valid, Cadence, Mentor, ECAD, VLSI, AMI and a host of others. And he has introduced more than three dozen EDA startups, ranging from the first commercial IP company to the latest statistical … More »
February 9th, 2012 by Ed Lee
To finish off our series of predictions, I would like to point you to another series of interesting and informative prophesies. Click on the following topics to see these predictions collected by Brian Bailey, Editor of EDA DesignLine.
Industry Trends
Tools
ESL
IP and Physical Design
The Bold Prediction for EDA
A big THANK YOU from Ed & me (Liz) to all who shared their eye opening predictions with us. Click on their names to see their predictions. Mike Gianfagna, Karen Bartleson, Paul McLellan, Jens Andersen, Bob Smith, Steve Schulz, Mathias Silvant, Herb Reiter, Max Maxfield, Chris Edwards, John Barr.
Only time will tell……
 The Persistence of Memory, 1931, Salvador Dali
Tags: 2.5D, 2012, 3D, 3D stacked die, Ansys, Atrenta, Cadence, Dassault, Double Patterning, EDA, EDA & IP, eda 2 asic Consulting, EDA DesignLine, EDA360, EdXact, Electronic Design Automation, Engineering & Technology, FPGA, Invarian, investment, IP, Lee PR, Lithography, low power, Low Power Design, Low-Power Design Blog, Magma, Maxfield High-Tech Consulting, Mentor, Needham, New Electronics, Programmable Logic, Programmable Logic DesignLine, publishing, Semi-wiki.com, Semiconductor IP, semiconductors, Si2, SoC, SoC Realization, social media, software, Standards, Synopsys, System on Chip, Tech Design Forum, textbooks, www.leepr.com
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February 1st, 2012 by Ed Lee
In 2012, we’ll see tablets and smartphones changing the world. That’s another way of saying Apple’s moves will have huge implications in semiconductors, foundries and EDA.
Apple’s use of the Samsung foundry has started an arms race between Samsung, TSMC and Global Foundries. Samsung is ramping up to meet the capabilities and capacity of TSMC. Intel is being pushed to stay ahead technologically and to consider new business models. Global Foundries continues to work to ramp its yields.
This situation will be good for semiconductor equipment and EDA vendors as well. Their tools will facilitate the new processes and the link between design and manufacturing.
Another element: in 2012, we’ll see the supply chain continue to consolidate. Why? The cost to design a complex SoC requires a big budget and a big market opportunity. Only the largest of semiconductor companies can tackle these designs. This increasing cost helps the FPGA vendors.
The foundries face increasing technology and capital requirements to move to new process nodes. Only a few will make it.
The public markets have been closed to EDA companies for a number of years making acquisition the most likely exit for EDA startups. Apache chose to be acquired by Ansys in 2011. It has been difficult for a new, large EDA competitor to emerge. This bodes well for Big EDA in its negotiations with Big Foundry and Big Semiconductor. In 2012 I believe there are several EDA companies poised to go public.
Who will be the beneficiary of these changes in 2012? Apple. Consumers should also benefit as new, leading edge fab capacity will be used to make exciting new devices.
John Barr
Portfolio Manager
Needham Aggressive Growth Fund
Needham Growth Fund
445 Park Avenue
New York, NY 10022
(212) 705-0462
Tags: 2012, Ansys, Apple, EDA, EDA & IP, Electronic Design Automation, Finance, foundries, Global Foundries, Intel, investment, IP, Lee PR, Needham, Samsung, Semiconductor IP, semiconductors, SoC, System on Chip, TSMC, www.leepr.com
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January 30th, 2012 by Ed Lee
The main technical breakthroughs we can expect this year will probably revolve around double patterning in lithography as EDA companies try to optimize the technique for density and performance. And it will probably have knock-on effects way up in the design flow, forcing designers to adopt much more regular designs. But, unless EUV sees a major breakthrough, double and further levels of multiple patterning is something people will need to get used to.
Regularity is likely to become a feature of low-power design as well. Although it hurts effective density, the drive to cut power consumption will see much more use made of on-chip redundancy – we’ve already seen some of that in the nVidia Tegra 3 and the ARM Big.Little initiative. We could see those techniques begin to extend into ultralow power circuits using near or subthreshold devices as engineers discover how to model circuits effectively and recover lost performance at very low voltages. Some of these techniques will also help reinvigorate older processes – using better EDA to trim power consumption instead of relying primarily on process changes to deliver better energy efficiency.
Chris Edwards
Technology writer: Engineering & Technology, New Electronics, Low-Power Design Blog, Tech Design Forums
Tags: 2012, ARM, circuit-design, EDA, EDA & IP, Electronic Design Automation, Engineering & Technology, EUV, Lee PR, low power, Low-Power Design Blog, multiple patterning, New Electronics, NVIDIA, semiconductors, Tech Design Forums, Tegra 3, www.leepr.com
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January 25th, 2012 by Ed Lee
On the ASIC/SoC side of the fence: Reducing power consumption is becoming increasingly important — I anticipate that this is the year that power will finally come to the forefront of EDA tools — I know that they optimize for power now, but largely as a second thought — like synthesis, for example, optimizes first for area and timing and then for power – I think we’ll see a move to optimize for power as a primary consideration.
On the FPGA side of the fence: As we move to the 28nm node and below, radiation is increasingly of concern with regard to electronic devices. It’s no longer just of interest for aerospace applications — at these low device geometries, radiation can affect chips in terrestrial applications. FPGAs are particularly susceptible because in addition to their normal logic and registers and memory cells they also have configuration cells. In the past, the only radiation-tolerant FPGAs were antifuse based — but these are only one-time-programmable (OTP) and trail the leading edge technology node by one or two generations. SRAM-based FPGAs offer many advantages in terms of reconfigurability and being at the leading edge of technology, but they are more susceptible to radiation events in their configuration cells. My prediction is that we will see more and more efforts from FPGA chip vendors and EDA tool vendors with regard to creating radiation-tolerant designs.
On the personal side of the fence: I predict that people will come to realize that what the world needs is a book about creating radiation-tolerant electronic designs that can be read and understood by folks who DO NOT have a PhD in nuclear physics – a book that is of interest to the people who design silicon chips (both analog and digital), the people who create EDA tools, the companies who manufacture the chips, and even software engineers (have you heard of “radiation tolerant software”?). I further predict that someone will finally realize that I am the best person to write this book and will approach me with a really great sponsorship deal that will bring tears of delight to my eyes 
Clive “Max” Maxfield
Maxfield High-Tech Consulting
Editor, Programmable Logic DesignLine, EE Times
www.CliveMaxfield.com
Tags: 2012, ASIC, EDA, EDA & IP, EE Times, Electronic Design Automation, FPGA, Lee PR, low power, Maxfield High-Tech Consulting, Programmable Logic, Programmable Logic DesignLine, publishing, semiconductors, SoC, software, SRAM, System on Chip, textbooks, www.leepr.com
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January 24th, 2012 by Ed Lee
A number of 2.5D IC designs will hit the market and demonstrate both the value of 2.5/3D technology as well as the importance of powerful and user-friendly tools for “Pathfinding”, to quickly identify the best (lowest cost) implementation alternative.
Herb Reiter
President
eda 2 asic Consulting, Inc.
www.eda2asic.com
Tags: 2.5D, 2012, 3D, 3D stacked die, EDA, EDA & IP, eda 2 asic Consulting, Electronic Design Automation, IC Design, Inc., Lee PR, semiconductors, Standards, www.leepr.com
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