Piyush Sancheti of Atrenta brings up a good point: for Ip to work as we envision it can, what players have to contribute to the quality effort? And what does each player type need to contribute? http://bit.ly/gpAHI1
Archive for the ‘Uncategorized’ Category
I recently had a chance to talk with EDA veteran Jim Girand about what the Japanese market looked like for EDA and IP companies, especially startups. Jim has been in EDA since its inception. He’s been a sales executive with various EDA firms including SDA and Cadence, an angel investor, and continues to set up sales distribution channels in Japan for startups and mid-sized companies.
Ed: Jim, let me throw out an observation that may be totally off base. I say that a lot of the startups in our area bypass the Japanese market, preferring to get into the Chinese (mainland but also Taiwan) and Indian market first.
Jim: Well, Ed, I’m going to disagree with you there. It seems to me that there is a lot of potential upside to pursuing the Japanese market. The large electronic product companies do demand a lot from their design tool vendors but they also reward their vendors with loyalty and purchase orders. Of course the other Asian markets are potentially lucrative and will surely grab a larger percentage of the Asian TAM (total available market) over time. But the structure of Japanese sales has changed. It seems to me that there is a lot of potential upside to pursuing the Japanese market and Japan still has the largest EDA market overall among the Asia Pacific countries. The latest EDAC numbers show for Q3 2010, Japan alone was 18% of worldwide sales and all the rest of Asia Pacific combined excluding Japan was 21%.
Ed: Interesting. The distributors I knew of all seem to be gone except for Marubeni, Innotech and some smaller organizations. So let me ask: How has the Japan distribution channel structure changed in the past twenty years?
Jim: Well, let me set context first. A historical perspective may illuminate why the Japan distribution channel has evolved to its current structure.
Traditionally, there were two choices; a full service trading organization that bought and resold EDA products or establishing a ‘K.K.’, a separate corporate entity staffed with local people dedicated to the supplier.
Ed: What’s the role of a trading organization?
Jim: So, the trading organization –– or distributor –– bought the EDA tools at a discount, marked up and resold them with a sizable margin. The margin covered currency translation, local sales and applications support, cost of collection and other costs such as marketing and administration. Often, the trading company would make a ‘pre-purchase’ to encourage the supplier to give good support to Japan and designate a part time applications engineer who would be trained to conduct demonstrations and evaluations. Further, these trading entities often had excellent reputations and high level relationships that helped the small EDA company get an introduction at the large customers. As the supplier matured and grew, he had a choice of getting the trading company to invest in more infrastructure or start a K.K, that could assume all or share sales and support responsibility.
Ed: I do remember that the distributors like SC Hytech and that group of smaller firms had great reputations for service and support.
Jim: So over time, users pushed harder for prices that were comparable to those in the U.S. They began to implicitly – if not explicitly – separate the services offered and assume responsibility for some or just do without. Sophisticated IDMs and systems companies concluded they could buy in U.S. dollars, and get early technical support from the headquarters, especially with advancing information technology that made it possible. In this high pressure environment that squeezed margins, some full service trading companies left the business and at the same time smaller, more flexible organizations and entrepreneurs took their place. Also, organizations such as those offering design services and local design automation tools added small U.S. suppliers to their suite of products.
Simply stated, competitive pressure starting from the end users has driven the Japan distribution channel, today, to be heterogeneous and have a wide variety of selling organizations. Also, not to be forgotten, EDA suppliers are designing their products so mere mortal circuit designers can use them – quickly. And technical support is oriented more toward the most sophisticated applications.
The end result of this evolution in the Japan distribution channel is all good. The end users will always demand and get superior EDA tools and support. Full service trading companies will have to demonstrate their infrastructure, long term high level relationships, local technical support and administration are efficient, a better local value than the end user getting these services piece meal.
Ed: And what of the sales rep?
Jim: Likewise, the independent sales representative must bring a persuasive contribution through the services he offers, beyond a good price, that will cause the end user to exert the extra effort to buy from him. And, going forward, we can be sure of one fact. The pressure on margins, the cost of sales, will only get stronger and felt from the local representative to deep into the supplier, driving all parties to be more efficient.
Ed: So what’s the effect of these changes for the small EDA vendor?
Jim: Now, from the perspective of the small EDA supplier seeking a distribution partner in Japan these changes in the channel structure can have profound effects. Namely, with a traditional trading company the sales development resources are ‘in country.’ You should have a designated sales manager who is responsible for the local infrastructure and getting your products introduced to the ‘A’ level end users. You will need to establish quotas, sales plans and be responsive when more advanced resources are requested.
At the other end of the spectrum, an individual sales representative will need much more guidance and particularly, technical support to help establish and successfully conduct evaluations. The supplier should plan on traveling to Japan often, perhaps once/quarter, make joint sales calls, conduct seminars and establish a corporate as well as technological identity with the end users. A much more active sales management role by the supplier is required here. At this time, there is no evidence whether the traditional trading company model is more effective than smaller organizations. More important, the supplier should think about the above considerations and choose an organization that will be compatible with his emerging culture.
Ed: Interesting, Jim. So there is no one formula on how to decide which works best for each type of company?
Jim: Not really. It depends on the considerations I mentioned earlier, plus the rapport established during the interview process, convergence of each organization’s interests, complementary product lines and existing relationships with prospective end users.
Ed: For those reader with questions, can they get hold of you?
Jim: Sure! I’d welcome their questions.
Ed: Jim, thanks for taking time to update us all on what’s going on in the Japanese distribution side of the EDA business.
Note: Jim Girand can be reached at firstname.lastname@example.org, website: www.girand.com.
James F. ‘Jim’ Girand
Technology Strategies & Investments
Ron Craig, Senior Marketing Manager at Atrenta and an expert on the subject of timing constraints, was good enough to sit down with me (Liz Massingill) recently to talk about the subject—what the current problems are and how to fix them. This is the result of my interview with Ron.
Liz: Ron, I was shocked to see, in the survey you conducted, that 94% of designers have timing constraint problems that could stop their current designs dead in their tracks. But they also don’t see a way to change their current methodology. WHY?!?!?!?!
Ron: There’s certainly no doubt that timing constraints remain and will continue to be a problem for design teams. The irony is that even though timing constraints are repeatedly an issue, most of these design teams feel that they know how to address all the problems that typically arise. It’s almost that the problems are viewed as less severe if the solutions are known.
Liz: Seems like the problem is more about changing the mindset. But why are designers running into increasing clock domain issues in the first place? Use of more IP? Process nodes going down to the next level? More complex designs?
Ron: The key culprit here seems to be IP. With IP, the functionality is reusable but the timing constraints are often not. Third party IP developers may well be experts in what the IP is supposed to do but not necessarily its implementation, leaving design teams with incomplete and inadequate timing constraints. On the other hand, IP reused from another design may well have been constrained in a way that’s not compatible with how you want to use it in your chip – especially if you need to change how the IP behaves. In today’s designs where IP amounts to 70% or more of a typical SoC, you end up with the constraint-driven implementation process becoming increasingly risky.
The process shrinks and more complex designs mean you simply can’t get away with having inadequate timing constraints anymore.
Liz: Well, what can they, or more appropriately, their project managers or internal CAD departments do about this increasing problem?
Ron: The key is to introduce more certainty into the whole process. Rather than taking an optimistic, or reactive approach to timing constraints, it makes a great deal of sense to put some effort in up-front to make sure that they are good. Many of our customers have noted that they simply can’t deal with the number of iterations it takes to refine timing constraints during the implementation phase of their projects, so they’re working on finalizing them up front as part of their RTL handoff. The trick for project managers or CAD people will be to introduce a methodology that their front end teams (who aren’t necessarily timing constraint experts) can easily adopt, and this is where comprehensive automated solutions such as SpyGlass-Constraints come into play.
Liz: So why isn’t this happening? Seems to me that an ounce of prevention is worth a pound of cure, as they say.
Ron: Let’s look at the two camps. First of all you have the RTL or front end team, who historically don’t want to take ownership of any part of the implementation process (even they know the design well enough to define its constraints). On the other side of that handoff ‘wall’ you have the back end team who feel that their expertise in this area, coupled with whatever the implementation and timing tools complain about, is enough of a solution. So depending on which side of that wall you sit on, you may feel that it’s either not your problem….or not a problem at all.
Liz: But we know there IS a problem, and it’ll only increase. So where in the design flow should project managers look first for a fix?
Ron: There is often a perception that timing constraints can’t be fully defined until you are actually using them – until you are in the thick of implementation or timing analysis. The problem with this is that your constraints end up being written so that you can close timing, instead of being defined to set the ground rules for timing closure. A classic example of this is the definition of timing exceptions – they’re often defined to mask timing violations, but in most cases they’re not exhaustively verified. A timing exception is a design characteristic, so can be defined and proven up-front before the implementation process even starts. It’s like an architect finalizing the plans after the building is complete. If your objectives aren’t clear how do you know when you are done?
Liz: I see what you are saying—it’s like putting the cart before the horse. Stop me, Ron, if I use another one of these old sayings. I’m dating myself. So who’s out there with technology that can help change the methodology and fix the timing disaster that’s looming?
Ron: It’s been possible to do some rudimentary timing constraint analysis in a range of implementation and STA tools since the advent of timing driven optimization. The problem with this approach, however, is that it’s largely a reactive one, and as a result doesn’t help reduce the risks in your implementation process. More recently, vendors (often ones outside the implementation/STA space) have started to provide solutions that allow the user to check the correctness of their constraints before implementation. What we’ve done with SpyGlass-Constraints is to take it one step further and look how timing constraint analysis is part of the bigger picture of reducing implementation risk. A great example of this is how we use our constraint verification methodology to ensure that data such as clock setup is in good shape before you use it to drive clock domain crossing (CDC) analysis. Again, it’s all about finding the issues up front and reducing risk later.
Liz: Well it’s intriguing…a Titanic-like iceberg of a design problem out there and we’re forging ahead…like the Titanic?
Ron: (laughs) Indeed – though given that the Titanic was built in my home city I always feel the need to point out that this particular disaster came about as a result of pilot error! To take your analogy further, I guess that the ‘iceberg’ here is a failure to close timing. Better guidance will definitely help you avoid that one.
Liz: Who knew? (laughs) Well, where can we learn more about this problem and how to fix it? Oh…and your customer survey…can we get a look at that? Sounds like some compelling information in there.
Ron: Yes, the customer survey was VERY telling and gives us a good leg up on what designers need to close at RTL for the next several generations of designs. In its current form, because we talked to customers, we can’t release it.
However, Bernard Murphy WILL refer to it at length in his DesignCon panel.
Liz: What panel is that?
Ron: At DesignCon we will be holding a panel on: “The Same Chip Killers keep Delaying your Schedules – What are you doing about it?” moderated by Ed Sperling, editor of System-Level Design. The panelists will discuss a broad range of issues, including timing constraints, the impact of IP etc. that repeatedly cause schedule slips. It will take place on Monday, January 31 at 4:45 p.m.
Liz: Sounds like a crucial discussion. I’ll be sure to attend!
This is Liz here, and I’ve happened to notice recently that many of the bloggers I follow are not as prolific as they were a year ago, when blogging was all the rage. Is it just writer’s block as Karen Bartleson bemoans (in a lighthearted way, of course) in her recent blog or is there something bigger at work here?
What say you?
A couple of weeks ago, a client asked, in essence, “why comment on articles or blogs?”
OK, so he didn’t say it exactly like that. But he did say that he’s
…struggling to figure out what really makes sense regarding the growing amount of posting by anybody and everybody….Is all this writing and blogging serving a real purpose? I’m not sure. Some blogs get recognition and response….I think most don’t.
He’s got a point. I think bloggers (indie, company and editorial) all feel, in our gut, that there’s value. But how do we measure that value? What do comments add to a blog or article? Tough one.
So I asked some of the bloggers what they thought. First off, I went to one of the longest running bloggers in EDA – Karen Bartleson. (Is it really three years, Karen? She’s at http://www.synopsys.com/blogs/thestandardsgame). She shed really insightful light on why EDA blogs get so few comments, if we compare them to consumer blogs like Yelp. And, she has her blog up on what she’s seen in the three years since she started her blog. So do take a look at Karen’s analysis of EDA blogging. I bet she’s got a take on the state of EDA blog comments.
Karen’s, along with a bunch of other bloggers’ comments on EDA blog comments gave me some trends to ponder. Some recurring points:
__the honeymoon infatuation period for EDA blogging has come…and is going. Now there needs to be some sense of longterm value.
My take…just what is “value” in terms of EDA blogs? Different from perspectives of the client, journalist and PR person.
__some indie bloggers say they see their blogs as diaries, written for themselves and interested people.
My take…everyone is aware of a larger cast of potential viewers, however. (By and large, they value comments but don’t use it as a metric of their blog’s value.)
__there are more eyeballs on the blogs than we can ascertain.
My take… however, these numbers are impossible to get for viewers and bloggers hosted by other sites. There’s no SRDS* in the EDA & IP social media world.
*SRDS was (is?) an organization that certified reader numbers for print publications so that they could charge advertising rates based on readership.
__engineers by and large are pretty quiet, shy types who rarely will comment or extend a discussion, even if they do read the blog, article and their accompanying comments.
My take…this came up a lot. I’m not sure…would their shyness prevent them from commenting? Probably. Would the relatively anonymous filter of the comment field encourage them to speak out? Potentially.
__by and large, the number of comments aren’t an accurate measure of eyeballs.
My take…lots of agreement that some sort of metric on value is reasonable, understandable. Less agreement on whether it’s needed now.
(One person compared the dilemma to the old attempt to measure column inches to value, which measures volume but doesn’t take into account perceptual, qualitative value.)
__commenting is a lot like getting a quote into an editorially-written article insofar as creating an authoritative voice that gets recognized, over time, as an industry voice to listen to…or not, depending on the content of the comment).
My take…one especially insightful editorial blogger felt that comments are a dynamic part of a living, breathing article that encompasses new perspectives with new comments and discussion.
One difference that I see is that the editor or author of the article hasn’t vetted the comment or incorporated it into his or her article. The comment is a response to the vetted article, which is the insightful editorial blogger’s point, I now see.
__the blog (and blogger) or article (and author) and its comments, to some degree, form a community onto each of themselves.
My take…this discussion got a bit abstract for me but I hear the notion. Help!
__this is a good time to talk about the expectations of each community (indie bloggers, editorial bloggers, company bloggers) and how to sync up each community so that there is value for everyone.
My take…but it’ll require the different goals and expectations of each community to somehow sync up so that each community’s efforts bring value to one another. How does that sync up with goals and expectations of customers, clients?
Of course, there’s no answer (yet) to the question about value here. The bloggers (indie, company and editorial) feel that there is value in commenting. Many of them agree that no one can measure value right now but that there ought to be some way to do so. Most everyone thinks that there is an existing, intangible value of being a voice of authority, an industry citizen.
And everyone thought we ought to keep talking about this issue.
– end –
This is the 2nd part of my interview with Joe Gianelli, VP of Marketing and Business Development of the new start up…..InPA Systems.
Liz: Joe, can you give us a little bit of background on InPA’s founders, Thomas Huang and Michael Chang?
Joe: Both Tom and Michael are longtime EDA entrepreneurs, having founded a number of startups, bringing to InPA a wealth of expertise in logic emulation, rapid prototyping and RTL verification.
Tom is probably best known as a co-founder and CTO of PiE Design Systems. He continued on with Quickturn when it acquired PiE. He was also EVP and CTO of Aptix, a rapid prototyping company, and founded several other companies in the emulation and ATE areas.
Michael was a co-founder, CEO and president of Verplex, a formal verification company that was acquired by Cadence. At Cadence he served as VP and GM of the formal verification group. Michael also founded Checklogic, which was acquired by Mentor.
Liz: And how about yourself? What is your background?
Joe: I was involved in the successful launch and acquisition of Taray just before joining InPA. I have spent my entire career in EDA, making the rounds from Synopsys to Epic Design to Meta Software and to Cadence. I was at Synplicity for 10 years, where I was VP of Business Development.
Liz: That’s an impressive combination of experience and expertise that you all bring to the table. Did I notice some high profile names on your advisory board?
Joe: You sure did! Bernie Aronson, from Epic, Synplicity, Kilopass; Michel Courtoy, from Certess; Sean Torsney of Verplex, and Kazuyuki Kawauchi from Fujitsu.
Liz: So what are your initial target markets?
Joe: SoC projects using FPGA prototype systems to verfy and validate their SoC’s.. Right now, we’re focusing on North America and the major Asian markets. We’ll obviously be going into Europe shortly.
Liz: When can we expect to see your first product?
Joe: This really depends on the success of our beta sites, could be as early as late Q4.
Liz: Thank you, Joe, for giving us a little insight (or should I say visibility?) into InPA Systems. I’m sure we’ll be hearing more and more about InPA and Active Debug in the near future.
Liz Massingill interviews InPA’s Joe Gianelli
This month, a new company announced its entrance into the rapid prototyping space. It goes by the name of InPA Systems. I was lucky enough to be able to grab a few minutes with its VP of Marketing and Business Development, Joe Gianelli, in order to learn a little bit about this new start up, its exciting new technology and how it could impact the future of rapid prototyping.
Liz: InPA….not an obvious name. What does it stand for?
Joe: Yeah, that’s an obvious question. It stands for integrated prototype automation, which are the characteristics of the technology we bring to the market.
So what InPA Systems is integrating is the RTL simulation and FPGA prototyping environments and automating a critical portion of the “bring up” that verifies that the mapping of the RTL code into the multiple FPGAs correlates to the original RTL code.
Liz: So InPA is in the rapid prototyping area, a segment that’s been around for, what, 20 years? What do you bring to the market that’s new?
Joe: InPA’s mission is to more fully harness the power of today’s FPGA rapid prototyping systems. Our most noteworthy technological capability is bringing debug visibility to users – who used to have to fly blind.
Basically, Tom (Huang) and Michael (Chang) saw the need for a more complete rapid prototype environment that integrated today’s RTL verification and rapid prototype environments with better visibility.
Liz: So technically, how does this work?
Joe: Without getting into a technical schpiel, InPA Systems integrates the RTL code and FPGA prototype environment so that engineers can debug in their RTL code while accessing their captured faulty conditions with full visibility. The automation here is to cross-link the RTL code with the captured faulty condition and to expand full signal visibility around the faulty condition.
We’re also enabling full system debug. This is when engineers are integrating the software and hardware design components enabling engineers to catch issues easier when integrating both HW/SW in the FPGA prototype environment. The automation here enables full system debug with “active debug” technology to dynamically control HW and to cross-trigger between FPGAs.
And finally, we’re automating the full capture of faulty conditions across multiple FPGAs. Today, engineers must capture and debug one FPGA at a time.
Liz: That’s got to be key! Why is it important or noteworthy to integrate and automate this?
Joe: It’s extremely tedious and difficult to isolate a hardware problem when it spans RTL code over multiple FPGAs. Giving the engineer the ability to fully capture the faulty scenario leads to much quicker isolation of the actual problem.
Liz: What does this new technology offer to the user that he or she hasn’t been able to accomplish up until now?
Joe: Right now, engineers probe around in the dark looking for problems in the hardware, one FPGA at a time. We give them the tools to explore various scenarios without having to recompile FPGA place and route…this is a real pain for engineers today. And we give them full visibility around their problem, making it easier to detect and fix.
Liz: What does “active debug” mean?
Joe: It’s allowing the engineer to remain active in the debug process; forcing certain circuit states, capturing data at speed, analyzing the data, and essentially remaining active in the debug process as opposed to probing around in the dark and waiting for another FPGA P&R iteration. What we call Active Debug is a combination of technology and methodology that increases the productivity of engineers who are integrating hardware and software and validating in-system with a rapid prototype .
Liz: So it’s an answer to the old debug visibility problem, right?
Joe: You got it.
Liz: So I have to ask, how is it different from existing debug? Passive debug, is it?
Joe: Yes. As most current systems use the passive debug approach, they only probe the circuit looking for possible problems with limited visibility, which doesn’t allow the user to dynamically create different conditions in the circuit that allow for testing of those conditions while running in the FPGAs.
In contrast, active debug allows the user to force various conditions in the circuit, capture over multiple FPGAs, analyze in a user friendly simulation environment, while reducing the number of FPGA P&R iterations.
Liz: Why is it important to debug in your “active” mode?
Joe: One of the biggest challenges of the SoC design team is debugging problems when integrating SW and HW together. Today, most SoC design teams are integrating their SW and HW on FPGA prototype systems and using the debug tools from the FPGA vendors which were not architected to debug large SoC designs over many multiple FPGAs. Consequently, engineers are not very productive using these tools as they search in the dark, one FPGA at a time, with limited visibility. Allowing engineers to become more “active” in their debug process moves them closer to isolating the bug much faster. It’s really allowing them to do their jobs much more efficiently.
Liz: I’m trying to hone in on the visibility function InPA brings to designers. What do you mean by “visibility” and how is that different from current prototyping methods again?
Joe: Visibility is really two things. First, it’s allowing engineers to capture their faulty conditions over multiple FPGAs as opposed to one FPGA at a time. This gives them much greater visibility into the potential problem. Secondly, our technology expands all the signals in the captured scenario giving engineers full signal visibility.
Part 2 of this interview will air on September 6.
The pre-DAC acquisitions of Denali and Virage drastically realign the core of the EDA industry. When IP first came on the scene here in the US, (I think 3Soft was the first IP company I saw), many people figured that IP would become another form of delivery for chip designs – and that they would come from the semiconductor companies.
The EDA executives’ explicit remarks about how IP is key to their continued growth could turn EDA into an industry of IP haves and IP have nots.
How does this EDA realignment affect customers? We asked Atrenta vice president of marketing and industry voice Mike Gianfagna, ” What does the EDA industry realignment mean for customers?”
Here’s what he said:
Realignment can mean two things that are related, but a bit different.
One form of realignment we’re seeing is the IP market merging into the EDA market. This is definitely good for IP customers. Effective IP reuse requires a blend of quality, highly validated IP and a good reuse methodology. The methodology need is for both authoring IP to be reusable and implementing the reuse itself. EDA is a good place to bring all this together. Most larger EDA companies understand what it takes to deliver high quality, validated designs. They also understand what a reuse methodology should include. A lot of the smaller IP shops don’t have this perspective.
Another realignment is the “annexation” of embedded software into EDA. Synopsys is validating this trend with their buying spree, and Cadence is validating the trend with their EDA360 proposal and some buying, too. This is also good for the customer. If software development teams can help to drive the silicon creation process, we are going to see some new killer apps emerge as a result.
What do you think about the combination of IP and EDA? Let us know in the “comments” section.
– end –
Qualcomm’s Riko Radojcic clearly was the point person on the joint effort. After all, he was the customer specifying what his intriguing PathFinding vision and technology had to be and become….and he’s been working on this for QUITE a while. Radojcic noted that while the promise of 3D is high and sets expectations about a new level of design, the reality is that the technology to achieve 3D design is broken. That’s how he embarked on the definition and realization of Qualcomm’s PathFinding vision and technology. He heads up the Qualcomm PathFinding technology effort.
Atrenta, imec and AutoESL collaborated to create what Qualcomm thinks is the first working 3D flow. While it’s incomplete – only HLS and early estimation tools are included right now – Radojcic said it has started him on realizing the PathFinder vision. He said that he certainly needs HLS and early estimation tools and that gets him started. He needs early estimation to find the sweet spot for a chip’s architecture and the technology for those leading edge designs Qualcomm designs. BUT this first version of the flow will need more tools and a lot of support by the time the 3D design demand hits in 2012.
The presenters kicked off the event by defining what 3D is. They agreed that with 3D design, you mix and match into one vertical step. Easy, right? Well, not quite. All of them recognized that the complexities of 3D require that you get it all right up front. And that is harder than anyone thinks.
The presenters agreed that a lot of work needs to be done to realize Radojcic’s PathFinding vision, of which 3D is a big part. But the tool vendor partners also saw it as an opportunity for them and the EDA vendors as well.
– Liz Massingill
We asked three EDA figures to comment on how the Synopsys purchase of Virage would impact the EDA and IP industries. Here’s what they said.
This acquisition puts Synopsys squarely in the front of the pack as far as IP suppliers go. This trend could be quite significant. Successful IP reuse is a combination of the right EDA tools, best practices methodology and well-designed IP. The EDA vendor is a pretty good place for all that to come together. ARM remains the exception to this rule, and several other rules for that matter.
Vice President, Marketing
I don’t see how this doesn’t make Synopsys a competitor with ARM on physical IP and ARC processor. ARM should start feeling like it is getting surrounded by Synopsys.
With EDA trying to expand its scope and grow beyond its traditional boundaries (see EDA360), and with small and medium size IP vendors struggling to grow, basic economy forces are pushing this trend.
Synopsys has already been a formidable IP player and Cadence now entered it with its recent acquisition of Denali.
There are still plenty of smaller IP players so we’ll see further consolidation playing out. The IP segment has been trying to define and position itself between EDA and semiconductors. We all wondered if IP would become an intrinsic part of the semiconductor industry, the EDA industry, or stand on its own. These days we clearly see that the IP pendulum has shifted toward EDA.
The outlier is of course ARM which is a different beast, in some ways closer to semiconductors: i.e., look at how ARM competes with Intel. With a market cap equivalent to Synopsys and Cadence put together, ARM is simply too big for that.
– end –