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Hogan & McLellan….show you the money

Friday, May 27th, 2011

How are you going to

SHOW ME THE MONEY

In EDA?

Get the answers from noted EDA & IP investor Jim Hogan and Paul McLellan – industry pundit and editor-in-chief of DAC Knowledge Center – as they define the new path to prosperity in EDA & IP.

Jim and Paul will give a short presentation and steer an audience-oriented discussion on what direction startups and established companies in the EDA & IP space ought to steer if they want to show their investors the money.

What direction? SOC Realization…no longer just a vision.  It’s the sweet spot in EDA & IP – where to invest and where to anchor your EDA/IP startup.    So if you are contemplating starting up or re-igniting a company in the EDA & IP space, this session will help you think about how your technology will analyze and verify design concepts much earlier in the design process…at much higher levels of abstraction than before.

Where’s the opportunity? SoC Realization as a cockpit to guide a design from concept to implementation, ensuring that the design is synchronized for both the hardware and software aspects of the system’s functionality.

What’s the upshot?
These changes in the SoC Realization supply chain will alter the 1) relative values of the chain’s components and 2) ability to leverage that value into profit. SoC Realization will revalue every entity in EDA & IP – the company you want to start up, or the one you’re working for.

When: Monday, June 6, 10-11am

Where: DAC, Room 24A

Please RSVP: Liz Massingill, liz@leepr.com

For more information, contact Liz @ 831-345-4702

 

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Show me the money

Monday, May 16th, 2011

Jim Hogan & Paul McLellan challenge the EDA industry to……

Show me the money

on DAC Free Monday

 

I’m jumping up & down with excitement?   Are you? Then see details below…..

 

Who: Noted EDA & IP investor Jim Hogan and Paul McLellan – industry pundit and editor-in-chief of DAC Knowledge Center

What: Define the state and future of, and path to prosperity for EDA & IP industry.

Format will be a short presentation, then audience-oriented discussion on what direction startups and established companies in the EDA & IP space ought to steer if they want to show their investors the money.

Why: This session will help attendees think about how their companies’ technology will have to analyze and verify design concepts much earlier in the design process…at much higher levels of abstraction than before.  That’s where the money in EDA & IP will be in the coming years.

Hogan and McLellan will propose that EDA & IP companies will have to help users guide their SoC designs from concept to implementation, ensuring that the design is synchronized for both the hardware and software aspects of the system’s functionality.

What’s the upshot?
These changes in the SoC realization supply chain will alter the: 1) relative values of the chain’s components;  2) ability to leverage that value into profit; an 3) valuing of every entity in EDA & IP – the company you want to start up, or the one you’re working for.

When: Monday, June 6, 10-11am

Where: DAC, Room 24A

Please RSVP: Liz Massingill, liz@leepr.com, Lee PR

 

For more information, contact Liz @ 831-345-4702

 

 

 

 

 

DAC frenzy is hitting!

Wednesday, May 11th, 2011

We’re 25 days and counting to the annual industry conference, DAC. As always,  people are talking…what’s the theme this year?  This young man has an idea…..

Click here to find out what it is

Last year, EDA360 was the at- & post-DAC talk of the town, so to speak.  So is there any continuity this year?

Atrenta seems to have made the first move in making the EDA360 vision real.  It’ll come out of the chute as “The SoC Realization Company,” and probably show technology that implements SoC Realization. By doing that, Atrenta may end up helping define the industry direction on how the EDA360 rubber meets the road.

Here is a white paper that talks about HOW to realize SoC Realization:

Click here to read the white paper

………………………………….

Stay tuned………next week, details on how to find out what Jim Hogan and Paul McLellan have to say about the direction EDA ought to follow so EDA & IP companies can answer their investors who demand that they “Show me the Money!”

 

Riko Radojcic on 3D standards

Monday, April 11th, 2011

Liz and I sat down with Riko Radojcic of Qualcomm to hear his thoughts on how upcoming 3D design and manufacturing would affect the EDA world.    Naturally, the conversation morphed into a discussion about standards that will be required to make 3D adoption pervasive.

Liz: Thanks for taking the time out of your busy schedule to sit down with us, Riko. So let me ask you, what is the relevance or importance of standards in adopting 3D?

Riko: Well, first, let me make a general statement about standards.  Sometimes some of the EDA companies view proprietary formats as a source of competitive advantage – a way of locking in a customer base.  This is especially true when a given company has taken a lead with a given solution, and they fear that opening up a proprietary format would shrink their slice of the market pie. However, in general, design standards, or standard exchange formats, or standard models, tend to make the whole pie bigger, as opposed to affecting the size of any one’s slice of the pie. So, in the long run, standards are good for users, like Qualcomm, and for vendors, like the EDA companies.  I keep referring back to the industry experience with SPICE models and the transition from the proprietary ‘Level 28’ model to the open standard BSim generation of models.  I think with all the brilliance of hindsight, the industry has benefited from an open standard model.

For 3D technology specifically, we are promoting the concept of standards, in order to accelerate the adoption of 3D design and manufacturing methods.  We want to help to line up the supply chain behind the 3D technology. I would say that most people – users, industry observers, EDA vendors, etc. all perceive 3D technology as a disruptive change.  The fear of that change is part of the barrier to adoption.  Standards are the other side of this coin of fear.  They bring down the feeling of fear.

Ed: Is 3D more a barrier to standards?  Are we sabotaging our own efforts?

Riko: There is a lot of FUD in 3D.  It is important to realize that there is 3D and then there is 3D.  Some future 3D implementations – like stacking logic on logic – does require disruptive change in design tools.  We will need design methodologies and tools that comprehend entirely a new dimension of parameters for this class of designs, and until these are developed, standards may even be a bit of a barrier.

On the other hand, 3D in the short term means heterogeneous stacking, like memory on top of logic.  So right now, 3D is not that disruptive.   We only need some minor upgrades to design logic in a smart way, to make stacking DRAM on top of it easier and lower risk. For this class of designs, standards would be extremely helpful – having a standard exchange format so that we have relevant information about die A when designing die B or vice versa would be excellent.  For example designing power distribution network on die A needs to know about power demands on die B.

To accelerate and facilitate adoption, we need more design information.   JEDEC for example is doing a nice job of working on the standards for memories

Liz: What is JEDEC doing?

JEDEC is defining the pin assignment and the pin array configuration required for Wide IO DRAM memories to be stacked on logic die.

Ed: What of vendors’ fears that buying into this format will be giving away too much of their own design data?

Riko: We can all make an investment in a standard format that can provide the right characteristics without exposing too much information.  The emphasis is on format, rather than specific content – which should be proprietary.  Again I like to refer back to SPICE and BSim models – where the model format, units, etc. are standardized, but the specific coefficients in the model are proprietary information of whoever owns the process technology.

Liz: Why is this not happening now?

Riko: We are all driven by financial motives.  No one feels they will make enough money out of it right now – and this is especially true for standards, which, by definition, belong to everybody. However, there could be certain advantages for someone creating a standard and then giving it away.  If you make the rules, you have a better chance of winning the game.

The thing that is required is a series of standard ‘exchange formats’ that would communicate the necessary information about the design of the various die to be stacked,  such that 3D stacking of these die is a low risk enterprise.  Basically to communicate design attributes such as power demand characteristics, thermal and mechanical stress sensitivities, maybe some floorplanning restrictions, etc..

Most of the standards bodies don’t have the capability to develop such standards. They have mechanisms to review a proposed standard and to manage and distribute it afterwards – but not to do the engineering required to develop one.  So, there’s a lack of champions willing to put in the work to develop and promote a standard.  It could be an EDA company, like Apache, or it could be an institution, like IMEC, or it could be an academic entity.

There are some activities going on, though. IMEC is working with Atrenta to develop a PathFinding tool – which may also involve developing a PathFinding exchange format.  Apache has taken the lead in pushing a standard power exchange format for 3D. Perhaps some of the academics could be engaged to develop standard exchange format proposals?  Si2 is willing to take a role in managing the standards, but someone needs to give them something to standardize.  GSA is active and willing to coordinate the discussions. But someone needs to make a proposal so the industry can say “I like it” or “I don’t like it” or whatever.

Liz: So you are looking for another EDA guy to come up to the plate, and then what if someone like Cadence comes up with a competing idea?  Then what?

Riko: Once a product is developed, all the EDA companies are invested in one format or another.  We want to get these standards in front of the product development curve, so that it would be easier for any one company to adopt and comply with a standard, rather than  making up their own format.  This is where the users – such as Qualcomm – come in.  We have the responsibility to demand this.

Ed: So it sounds like so far, we have a lot of discussion, but to a certain extent, some organizations are waiting for others to discuss or define a proposed set of 3D standards.   Other organizations are waiting for that proposal to get adopted before implementing the 3D standards.   How do we get off this merry-go-round?

Riko: I would say, let’s take a stab at partitioning the effort.  Qualcomm proposed this last September, at a SEMI/Sematech sponsored meeting in Taiwan.   We proposed dividing the world into two buckets…one set of players and activities focused on design related standards,  and another for manufacturing related standards. For each bucket of standard related activities, we proposed a suitable existing standards body, a suitable forum for discussion, and a suitable set of champions who would propose appropriate standards.  In the manufacturing domain, it would make sense to use SEMI to manage the standards, and Sematech to provide the Proposals. In the design domain it would make sense to use Si2 to manage the standards, and EDA or academics that are involved with EDA to provide the proposals. That way there would be less overlap and hopefully fewer gaps

Liz: What would happen then?

Riko: In addition, we proposed to create a forum which would be conducive to exploring and kicking around some of the proposed standards.  Standards bodies, by definition have a formal review and balloting mechanism – which tends to be slow.  So, in order to accelerate the discussion a separate forum would be nice.  The Sematech 3D Enablement Center is doing this already for manufacturing-oriented standards.  Let’s work with GSA to create a forum to discuss design-oriented standards, and if (or when) a given proposal is flushed out, give it to Si2 to create a true standard.

Liz: Your 2011 hope or wish for 3D standards?

Riko: That our industry can actually define a standard without having to fight a turf war.   We can do this if we get ahead of the 3D product curve.  But only if we all pitch in.. .

Riko Radojcic, who has over 25 years in the semiconductor industry, is a Director of Engineering at Qualcomm, currently leading the Design-for-Through Silicon Stacking Initiatives.

 

 

 

No New Startups? WTF?

Monday, April 4th, 2011

Last week, I had a running e-conversation with several folks – from academia, the angel community, bloggers, reporters analysts – about what new EDA and IP startups were out there. “New” being less than a year old.

One person more or less said,  “aren’t you working with a new prototyping startup?  That’s about the last one I’ve heard of.”  Another person, the academician, said that there were none, that the startup groundswell was in cleantech and software apps.  No one could think of a single “new” startup in our space.

Why?  Not why they can’t think of any new startups, but why none are out there or are so hidden that this group knows of none?

Lots of reasons come to mind.  Yeah, the big guys offer all-you-can-eat licenses and crowd out the opportunity for startup point tools; the financial community doesn’t see a decent ROI and don’t fund EDA and IP (although it looks like EDA can once again utter “IPO”  without derisive eyeballs rolling); EDA is mature and there’s only incremental improvements to be made, thus no great leaps any longer.

So are we wrong?  Are there new startups out there?  What technology areas?

– end –

What if….no more big three?

Monday, March 28th, 2011

Continuing with my conversation with Tom Kozas, president of CADmazing Solutions, I asked him about a hypothetical scenario:

 

Ed:   So Tom, what would happen if for some reason, the big three EDA vendors all went away?   So instead of Cadence, Mentor, Synopsys,  the biggest three would be Magma, Apache?  Atrenta?

Tom:  I think this raises even more questions.

Ed:  Hmmm…interesting.  What questions?

Tom:   Several come to mind:  Would this mean renewed growth for the industry? Would the fundamentals change that encourage investment in new startups? Would the design flows become more or less integrated, collaborative, and global?

Ed:  Ok, good questions to ponder.   So what would be THE big issue?

Tom:  The “Silicon” in Silicon Valley is missing.  Without investment in new semiconductor startups, growth simply won’t happen.  Virtually all new design starts are happening within the big systems and semiconductor companies which means the only way to grow an EDA company, is to steal market share.

But would this translate to increased value for the remaining EDA companies in the eyes of the financial community?  What’s interesting about this hypothetical is, even though it would put the remaining EDA companies in a position to take advantage of this opportunity they might not be able to.

Ed:  Just to play devil’s advocate, why wouldn’t that next set of players, whoever they are, be able to take advantage of the sudden disappearance of the big three?    And who do you consider to be that next set of players?

Tom:  Good questions.   But let me respond by saying what they will need to provide.

So, the next big three will have products that have great user interfaces, provide online collaboration, and be part of a new ecosystem that enables innovation.  The industry already has advanced technology but needs graphical and command-line interfaces that exploit the online design environment.

Second, designers don’t necessarily sit in the same building but often have to work on the same problem. For example, two or more designers should be able to share the timing database and bring up the same timing path without having to rerun static timing analysis and do it within minutes no matter where they are in the world.

Finally, the current EDA ecosystem is in the dark ages, there needs to be a new model that facilitates new algorithm and tool development with a reward system.

Ed:  Tom, thanks again for your insights.

 

Three Shifts for SIP

Tuesday, March 22nd, 2011

Ken Brock is the Product Marketing Manager for DesignWare Logic Libraries at Synopsys.  Ken shared with us here his view of the trends he sees for the future of semiconductor IP.

 

What Does the Future Hold for Semiconductor IP?

The marketplace for semiconductor IP (SIP) continues to grow at double digit rates. According to Gartner Dataquest, the number of third-party semiconductor design IP blocks in an average chip design will double from the current level and the SIP market will reach $2.3B in 2014. IBS and Semico believe the SIP market will be greater than $3 billion in 2014.

We see six major trends in IP:

  • Convergence: The increased demand for “Smart” consumer electronics is driving more features and functionality into a single device such as the latest craze in tablets shown at this year’s Consumer Electronics Show (CES). This trend is causing significant changes in SoC designs in areas such as power and performance requirements that drive technology node migrations, and in increased clock frequencies to keep up with bandwidth needs.
  • Core versus Context: Does this function differentiate the SoC? Interfaces like PCI Express® and USB have to work but they don’t generally differentiate the SoC.  As an IP vendor, we see many different applications spaces for our IP and we have to ensure that IP works over a broad range of configurations and products.
  • Fab-outsourcing: More outsourcing of manufacturing means more opportunity for customers to use off-the-shelf IP to meet their design requirements, and more demand for IP vendors to create high-quality IP on the most advanced process nodes.
  • Power, Performance, Area: As many semiconductor designs compete for the key sockets, having the fastest performance, lowest power and smallest area is often a key differentiator of the design with respect to processor performance, battery life, packaging cost and silicon cost. Choices of foundation IP (memory and logic) providers make a big difference between winners and also-rans.
  • Consumer-driven schedules: Shorter time-to-market and more features means that designers need to de-risk schedules by using high-quality IP solutions that have been proven time and time again in the market place.
  • Expense control: It is often less expensive for companies to buy third-party IP than to develop it themselves. This is particularly true in advanced nodes where the complexity of IP development increases rapidly with increasing data rates, restricted design rules and increasing variability. As an example, our estimate is that a 28nm standard cell and memory IP platform is at least five to 10 times as complex to design and verify as compared to a similar platform at 40nm.

With these trends as the backdrop, we see significant shifts in the SIP market as it continues to evolve during the next five years:

  • Most SoCs will have about 70 to 80 percent of their functionality in reused IP (internal and/or 3rd party). The majority of these IP blocks will be memories with thousands of instances per chip all connected with a variety of standard cell configurations. Optimized standard cells and memories can significantly impact the performance, power and area of a SoC.
  • Individual IP products will yield to more complex IP subsystems. These subsystems will include application-specific blocks and software. IP integration services will become increasingly important to validate the IP in the system context.
  • Multi-core designs will drive increasingly complex architectures. A virtual prototype of the IP and the larger SoC will enable earlier and more efficient development of application software and middleware.

This is a pivotal time for the semiconductor IP industry as companies strive to develop the best solutions to help designers accelerate their time from concept to implementation. These solutions generate value throughout the design chain by accelerating hardware/software integration and systems validation, allowing efficient SoC architecture exploration and optimization, creating and optimizing functional blocks, and using high-quality semiconductor IP. Designers are turning to trusted third-party SIP solutions to help integrate advanced functionality with the least amount of risk. Winners will choose wisely.

 

Tom Kozas on EDA in the Clouds

Tuesday, March 8th, 2011

I recently grabbed coffee with Tom Kozas, President of Cadmazing Solutions. Since Tom’s staff works with a variety of domestic and international electronic designers spanning many industries, he sees a lot of different attitudes toward design tools. So I asked him:

Ed: So Tom, what about EDA in the clouds? Do your clients see that as desirable? Even viable?

Tom: It all depends on who is realizing the value.

Ed: When you say “realizing the value,” what do you mean?

Tom: OK, good point. EDA vendors have a completely different reality of their product value than do their customers. The EDA vendors believe that their product provides “absolute” value while EDA customers only see incremental product value. At CADmazing we deal with this reality with every customer and vendor we engage with.

Ed: Why the vast discrepancy?

Tom: Well, it’s the customer that commits the extra time and effort to go from incremental to absolute value for the complete design flow. As for EDA in the cloud it won’t fix the EDA industry.

Ed: No? Why is that?

Tom: Large customers already have their own clouds accessed through virtual private networks. So if a customer’s design environment included tools from each of the three top vendors, would this mean they would have to log into three different clouds?

Ed: Well, would the EDA customers then create their own cloud interface that all EDA tools would have to work? Or that the big three could create a standard cloud interface?

Tom: I just don’t see this type of collaboration happening among the top three EDA vendors. The industry would need something like an “Open Cloud” initiative that enables customers to have access to any EDA tool they want, especially from EDA startups – once the world comes back to its senses and starts funding them again.

Ed: So what’s your take on when EDA will be in the cloud?

Tom: Some EDA companies are already offering their products on the cloud. EDA companies will need to be careful that they are not creating a solution looking for a problem.

If EDA vendors want to successfully offer their tools and services on the cloud, they will need to provide an advantage that increases their customers’ business success. A technical and/or business advantage that goes way beyond outsourcing compute cycles.

Ed: Tom, thanks for your take on the EDA cloud.
………………………………..

Tom Kozas is President and principal consultant of Cadmazing Solutions www.cadmazing.com and has worked for years in engineering and marketing at EDA startups – such as Monterey – and established companies – such as Hughes Aircraft, Cadence, Compass. Cadmazing provides IC CAD development & implementation services for analog, digital, and mixed-signal system-on-a-chip (SoC) technology and full-custom designs. Tom’s email is: tomk@Cadmazing.com.

DesignCon 2011: What was Different?

Friday, February 18th, 2011

turboSo what was different about DesignCon this year? Traffic and make up. There’s a new owner…EE Times.

What else?

1. There were actually people roaming the isles of the exhibit floor! So different from the last several years. It’ll be good to see the DesignCon numbers when EE Times, the new owner of DesignCon, releases them.

2. When I first walked onto the exhibit floor, I was perplexed. Not purely a show for chip designers?  Sure, EDA vendors were there, a couple of IP vendors. But test companies,
connector companies, material companies also!

I asked a couple of people. They acknowledged that the exhibitor make up was different. A couple of the people I polled said that DesignCon had morphed into a systems design or a PCB show. One person thought it had the makings of a complex FGPA design show.

What do y’all out there think?

­ – end ­–

Chip Killers: keeping design managers awake

Monday, February 7th, 2011

Am I gonna make tapeout in time?Liz and I attended a panel at DesignCon that asked the question: what are you doing about the chip killers that delay your tapeout? That’s an intriguing, possibly unanswerable thought, since we’ve asked that question virtually since EDA’s inception. Ed Sperling of Systems-Level Design moderated the panel which had on it: Sunil Malkani of Broadcom, Ravi Damaraju of Juniper, Ramon Macias of NetLogic, John Busco of NVIDIA and Bernard Murphy of Atrenta.

Sperling moderated a lively discussion; questions that he or the panelists or audience posed highlighted the ongoing nature, or unanswerability of the topic. Some were:

• As designers and design managers, what keeps you up at night?

• If your design has to finish in half the time that your previous project took, do you start with a [design methodology and flow] clean slate?

• How do you get hardware and software engineers to work together?

• What’s good enough to get the design out the door?

• How do you define failure?

• What’s the price of failure?

• Who owns quality?

• What do you do when your next project is 4X the size of your last design? Throw people at it? Make the tools do more? Run faster? How?

• How do I turn around a design in a month and get all of these [now-required] apps on it?

• Why does place & route have to be flat?

• When will P&R, timing analysis have to break down the design hierarchically?

• How can verification be improved so that its pessimistic estimates won’t require designers to over-design?

The panelists all bemoaned the dueling standards that plague EDA, attributing them to companies wanting to gain marketing advantage, to the detriment of EDA users.

Sperling will publish a transcript of this panel in a future issue of System-Level Design. Nic Mokhoff published a summary of the panel the next day.

Finally, I have a question: why does DesignCon schedule a management-level panel on a day when the exhibit floor isn’t open? Doesn’t help DesignCon panels’ attendance, which has been paltry for years, seems to me.

– end –

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