Sage Design Automation, Inc. announced its founding technology last month and created a lot of customer and media buzz at DAC’13 inAustin. I bet a lot of people were surprised that design rule manual creation and DRC deck implementation were manual, error-prone tasks – especially as we get into smaller process geometries – and that they can take years to put one together.
In a way, it’s a lot like writing a long paper on a typewriter, or even by hand. When you make an error, you use White Out (remember that?) or type back over the error with the erasing ribbon. There’s no way to correlate the paper’s index, spell check, grammar check or check for consistency.
So we accosted Sage-DA president and CEO Coby Zelnik to ask him about this problem, one that many of us assumed just took care of itself! Here’s what he had to say.
Liz here. I’ve just gotten word from Angel Orrantia of Innopartners, and we have a winner of the 2nd-ever hardware hackathon, mentioned in our earlier post today.
We’re waiting to hear from SKTA Innopartners LLC director Angel Orrantia on the results of the Open Compute Project hackathon that took place yesterday at the Facebook campus. Orrantia is one of the judges. We hear that the winner will be announced at the GigaOM Structure conference this afternoon sometime.
What happened at the hackathon?
There were a number of teams comprised of over 50 hackers from Silicon Valley, Singapore, Miami, Boston, Seattle, Virginia and Texas.
Projects included:
• building an ARM based system on a chip
• bringing robotics into the datacenter to automate repairs
• building a fast interconnect between ARM boards
• gathering server diagnostics data into a web interface for remote diagnostics over the web
• two projects on car automation
1- collecting diagnostic data about the car – like speed, fuel consumption, acceleration, etc. – to give people the ability to monitor their driving habits to prevent or avoid accidents
2- designing a headset that measures brainwaves to alert the driver or a third party company that can get in touch with the driver
Also, the winners from the last hackathon returned to continue working and expanding on their debug port aggregation hack.
In the following video, Warren Savage, CEO of IPextreme, talks with Mike Gianfagna, VP of Corporate Marketing at Atrenta, about collaboration – with TSMC and the Constellations partners.
Mike’s dream is for “a vibrant industry with a well-defined quality metric.”
KNTV, the Bay Area NBC affiliate, covered a story this past Friday on how Silicon Valley is the nation’s mecca for startups. KNTV reporter Scott Budman contends that Silicon Valley is stretching its borders north to Oakland. Really?
According to a survey conducted by the National Venture Capital Association, San Francisco is the nation’s hottest city for tech startups, with San Jose coming in second. Oakland is ranked at No. 11.
As part of this story, Budman interviews San Jose EDA firm, Atrenta, pointing to Atrenta as a typical Silicon Valley startup.
With less than 3 weeks away until DAC’13, Liz and I asked Warren Savage about IPextreme’s and Constellations’ planned presence there. Warren is not only founder and CEO of IPextreme, but also head of the IP consortium, Constellations.
We caught up with Warren recently, and Mike Gianfagna, VP of Corporate Marketing at Atrenta (Atrenta is a Constellations partner), happened to be there. So, the two of them let us in on what Constellations would be up to at DAC.
Liz: Warren, what play does IP have at DAC this year?
Warren Savage President and CEO IPextreme
Warren: Change is slow, but IPextreme and Constellations are happy to report change is afoot and our workshop at DAC serves as a prime example of this. Together with TSMC and our Constellations partners Atrenta and Sonics, we are pleased to present “Driving Quality to the Desktop of the DAC Engineer” on Sunday, June 2 from 1:00 to 5:00 PM. This workshop showcases a foundry, two IP companies, and an EDA company working together—exactly as we do every day.
Why, then, is this the first DAC workshop of its kind? Why have the ties binding us together in the semiconductor ecosystem not been highlighted before? Perhaps the old saying, “If all you have is a hammer, everything looks like a nail,” is the only explanation. At the end of the day, our customers need all of us – both IP providers and EDA vendors. We owe it to them not only to recognize that, but also to make their lives easier by working together.
The final word on the BIG theme(s) for DAC comes from Brian Bailey, Editor of EE Times EDA Designline……
For many people, the attendance numbers seem to be the number one issue on their minds this year. DAC has never been to Austin in its 50 year history and only once been to Texas. Yet there is, and has always been, a very large design community in that area, a group of people that have perhaps been overlooked. A head count seems to be a very unimportant number, even though it is an easy metric. But we are an intelligent industry that should know a lot about metrics and I think there are more useful metrics in this case, such as the number of first time attendees.
These two trend setters share their opinions on the BIG DACthemes in 2013.
I see two related trends:
1) More signoff activity earlier in the design flow
2) More focus on IP quality and usability
Both of these trends represent a maturing of design tools and business models. Because of the tremendous complexity that sub-20 nm design brings, it becomes more important to get the design right as early as possible. The tools are maturing in the earlier stages, and more designers are demanding clean reports, or sign-off level quality audits as a result. This is helping to reduce schedule delays and design costs – good for the industry.
Semiconductor IP is also maturing – both use models and business models. There is a growing focus on reporting delivered quality and robustness. This will allow IP providers that deliver the best IP to flourish. Also good for the industry. We’ll see an increase in conversations about IP providers collaborating with the rest of the ecosystem at DAC. Another good trend.
DAC is upon us….and in Austin, of all places – the island in the middle of Texas.
As it’s getting closer, we were wondering what the BIG theme is for the 50th DAC. So, we asked a few of our friends and colleagues in the industry. Here’s what a few of them had to say.
I expect DAC to continue to explore low power challenges, with much talk about solving FinFET issues at 14 and 10 nm. Then there is the ever expanding SoC and how to handle all of the challenges that come with greater integration and IP reuse. Finally, what’s DAC without a discussion of Moore’s Law and whether it will/won’t continue to define industry progress in the years to come?
