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Ed Lee
Ed Lee
Ed Lee has been around EDA since before it was called EDA. He cut his teeth doing Public Relations with Valid, Cadence, Mentor, ECAD, VLSI, AMI and a host of others. And he has introduced more than three dozen EDA startups, ranging from the first commercial IP company to the latest statistical … More »

What is in-situ de-embedding?

 
January 14th, 2016 by Ed Lee

As a follow up to Chris Scholz’s predictions on 2016 signal integrity trends, we checked in with in-situ de-embedding inventor Dr. Ching-Chao Huang, who gives us a more detailed look at how engineers will need to handle signal integrity measurement and calibration for high-speed boards.

huangEd:  When and why did you invent in-situ de-embedding?

Ching-Chao:  We first coined the term “In-Situ De-embedding” (or ISD) for the de-embedding software we launched in 2011.  It was a new approach to remove the non-causality artifact commonly found in other de-embedding methods.

Ed:  What was the problem you saw coming?

Ching-Chao:  Accurate de-embedding is crucial to characterize the electrical performance of a component, from chip to package, PCB, connector and cable.  A Vector Network Analyzer (VNA) is perhaps the best equipment to use for characterization because it measures the detailed electrical behavior of a component at every frequency.  However, a component, or device under test (DUT), does not usually lend itself to direct measurement and needs to be mounted on a fixture for connection to the VNA.  The effect of the fixture needs to be removed (i.e., de-embedded) in order to get the true electrical behavior of the DUT itself.

Ed:  So how did the electrical behavior get measured before?

Ching-Chao:  The traditional approach is to fabricate and measure test coupons that resemble the fixture’s lead-ins and/or lead-outs.  Information is extracted from the test coupons and de-embedded from the fixture + DUT measurement data.  To collect more information, the TRL (thru-reflect-line) calibration method requires that multiple test coupons be built.  This method takes up a fair amount of board space.

Due to the effect of fiber weave, etching and other variations, fixture and test coupons will see different impedance throughout the lead-ins/outs.  So de-embedding the fixture + DUT board with information derived from test coupons is akin to subtracting C from A+B and hoping to get A, where A is DUT, B is fixture and C is the test coupon.  In order to make C as close as possible to B, the conventional wisdom has been to use high-quality connectors and PCB material and tight etching tolerance, resulting in more expensive measurement.  Even then, engineers still get errors because it is not possible to make the fixture and test coupons identical in impedance at every location.  In addition, the larger the fixture, the more error accumulated.

The above de-embedding error occurs before and/or after DUT and eventually gets piled up into the extracted DUT results.  Such an error manifests itself as non-causality: the extracted DUT results predict that there is output signal before the input signal arrives.  This non-causal behavior is apparent when one converts the extracted DUT’s frequency response into time-domain transmission (TDT) or time-domain reflection (TDR).  In the frequency domain, such non-causality often appears as artificial ripples in magnitude and/or counterclockwise phase angle of scattering parameters (S parameters).

Ed:  Sounds like quite a problem, especially given the size and speed of board designs we’re seeing.  So what does in-situ de-embedding do to solve this problem?

Ching-Chao:  In-Situ De-embedding (ISD) takes a new approach to do de-embedding.  Instead of subtracting test coupons directly from the fixture + DUT, it uses the data of test coupons only as an initial guess for software optimization.  We chose the term “in-situ” to indicate that ISD identifies and de-embeds the true impedance of the fixture.

Ed:  What’s the advantage?

Ching-Chao:  Many advantages arise as a result.  The extracted DUT results are more accurate because they are causal by construction.  The measurement vs. simulation correlation becomes easier, so the design cycle time is reduced.  Less expensive connectors and board material and looser etching tolerance can now be used, resulting in cost saving.  A production board, instead of customized characterization board, can also be de-embedded directly.  ISD’s new methodology is a paradigm shift, and many industry powerhouses have already embraced it.

Ed:  Who uses AtaiTec’s in-situ de-embedding technology?

Ching-Chao:   Many telecom, IC and connector companies are our customers.  We also partner with Rohde & Schwarz to bring smooth user experience to their VNA customers.  Many will attend DesignCon next week.

Ed:  AtaiTec will be there too, I presume?

Ching-Chao:  Yes, at booth 755.

Ed:  So people who are curious or interested in in-situ de-embedding can stop by your booth and discuss it with you?

Ching-Chao:  Yes, of course!    I look forward to any questions, comments and discussion.

Ed:  Thanks for describing this technology to us.  See you at DesignCon!  What days will the exhibit floor be open?

Ching-Chao:  The Expo Hall will be open January 20 and 21.  The conference begins January 19.

…………………………………………..

Dr. Ching-Chao Huang is CEO of AtaiTec Corporation (San Jose, CA).

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