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Archive for March, 2014

Real RTL Signoff™ is a Comprehensive Signoff

Monday, March 17th, 2014

RTL Signoff is certainly one of the hot topics in chip design circles lately, and one that is garnering great interest and concern.  I chatted recently with Piyush Sancheti, VP of Marketing at Atrenta, on what it is, why it’s a design imperative, and how it should be done.

Liz:  Piyush, thanks for taking the time out to chat with me today on this vital topic…RTL Signoff.

Piyush:  No problem, Liz

Liz:  So, to start out, what is RTL Signoff?

Piyush:  “RTL Signoff” gained momentum as an established concept in 2013. While the concept is not new, a commonly-accepted definition did not exist in the past, which is now beginning to emerge.  Here’s what I think RTL Signoff is: a comprehensive series of well-defined MUST-pass requirements for your RTL before you commit the design to downstream implementation such as synthesis and physical layout. In addition to this complete set of RTL Signoff requirements, you need tools and methodologies to meet the requirement, along with tangible metrics to measure your pass/fail criteria.

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HOW will EDA/IP get beyond the horizon?

Sunday, March 16th, 2014

Brian Fuller -­ editor in chief of the now-lamented EE Times during its best years ­- and I were talking about it being great that there are these predictions about where EDA/IP is going in 2014. Chris Rowen’s wrap up prediction talked about EDA’s need to move beyond component – level focus. Chris isn’t alone in this idea.

The question is:  HOW will EDA/IP get beyond the component level and start looking at what’s beyond the 25-year EDA horizon and how EDA can and must add value.

Brian and I would love to hear what readers out there think…..

Does EDA & IP need to go beyond?

Where does it need to go?

And how will it get there?

How do software and hardware come together?

Wednesday, March 12th, 2014

Software is beginning to take on a bigger role in the SoC design world.  How do we get to SW-HW co-verification? This topic was the center of discussion at a private event last week co-located with DVCon.  The event, hosted by Jim Hogan and sponsored by Vayavya Labs Pvt. Ltd., included a panel discussion with Frank Schirrmeister (Cadence), Tomas Evensen (Xilinx) and Parag Naik (Saankhya).  George Lotridge of VMware and Michael Bair of Intel also gave presentations. Click here for the presentations. (more…)

Predictions 2014: Chris Rowen talks EDA and IP….and Beyond

Monday, March 3rd, 2014

For our final entry to this series, let me just reiterate our original question…..

What do EDA and IP (as an industry) need to do in 2014 to serve its user base better?

Chris Rowen, Cadence Fellow and Tensilica Founder, will wrap it up with his word on the subject.

“What does the EDA and IP industry need to do in 2014? Simply put, we need to move past EDA.

Let me explain. As an industry, we’re not just about ‘how’ you design something; we’re increasingly about ‘what’ you design.

This comes amid the relentless march of design complexity. It also comes as companies reconsider their position in the electronics ecosystem to try to deliver more value for customers.

For instance, semiconductor vendors are considering where they best fit into the design spectrum and they’re also looking farther upstream to understand market requirements of their customers’ customers. IP providers, for their part, are looking upstream to understand marketing technology requirements better and re-engineering their business models.

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