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Ed Lee
Ed Lee
Ed Lee has been around EDA since before it was called EDA. He cut his teeth doing Public Relations with Valid, Cadence, Mentor, ECAD, VLSI, AMI and a host of others. And he has introduced more than three dozen EDA startups, ranging from the first commercial IP company to the latest statistical … More »

Predictions 2014: Saankhya’s Anindya Saha on what EDA/IP vendors need to do for their users

February 6th, 2014 by Ed Lee

Anindya Saha, Associate VP (VLSI) at Saankhya Labs, shares his insights on what EDA and IP vendors need to do for their users in 2014. 

“Today the EDA and IP companies alike are in the race to cater to the big semiconductor players by offering the greatest IP in the latest process geometries. However, semiconductor startups, – such as Saankhya – do not change process nodes very quickly because it may not necessarily make business sense.  Here is why.

‘Process design margins’ is a fact of life, which we need to add when we use the latest process nodes. Incorporating these design margins simply adds to the overall SoC design cycle time which we want to keep to a minimum. Hence staying with the older process nodes may be a more prudent choice. When we look at the IP domain, we can categorize the available IPs into the following buckets – Analog IPs, Standard Cell and Memory IPs, Processor Soft Cores and Connectivity IPs.  Besides the usual PPA (Power, Performance and Area) metrics, what we look at for each of these categories is the metric of Power Efficiency. This metric can be based on mW/Mhz or in some cases mW/sq. mm depending on the kind of tradeoffs which we intend to do at System level.

The following are some of the issues I feel EDA and IP companies should address, especially in the domain of standard cell and memory IPs which are commonly used in almost all ASIC Designs today. 

System Centric Approach:

On the standard cell IP front (especially when we purchase from existing vendors), we find them optimized for power or performance but not necessarily both.

This is primarily happening because most of these vendors have not started looking at these components from a system-centric viewpoint and always want to cater to the lowest common denominator. A very simple example of this is the non-existence of wider multi-bit flops or latches (especially widths of 8bit or higher) in a standard cell library which would be superior in terms of area, power and performance as compared to an implementation done using discrete flip-flops or latches. Similarly components like transmission gate based multiplexers and datapath elements and pulse triggered flip-flops need to become available for wider usage to improve the Power Efficiency of the overall implementation. With SoC designs having more processing capabilities than ever and the constraint of targeting Lower Power, standard cell IP vendors must provide these types of components.

Countering Process Variability:

Today, designers face ‘process design margins’ as an issue for which there is no quick-fix solution. Teams across the world have their homegrown recipes for countering this. Fundamentally, we need to rethink the standard cell architectures and see how to design them with some degree of process variation immunity. This kind of variation-aware design has been practiced in the analog world and should be done in the digital world as well. Since EDA/IP Companies today have good contact with Foundries, proceeding on this vector should be possible.

A process variation immune component can minimize (if not completely eliminate) the burden of introducing design margins which could also end up as wasted area and power. As a side effect, when we address this issue, there is a unique upside because we will be shaving off several time consuming analyses, which all SoC designers religiously follow before taping out the chip.

What I would throw as a challenge for Standard Cell IP designers across the globe is to look at creating architectures which are process invariant with respect to timing? This is the need of the hour!

Low Power Memory Designs:

Embedded SRAMs need to have more flavors of power-efficient architectures. Shutting off the internal clocks of the memory core to prevent unnecessary pre-charging of Bit/Bitbar lines when there is no read access is one of the ideas which should be easily implementable. Similarly ‘smart shut off’ of internal peripheral circuits should now be the mainstream instead of asking SoC integrators to incorporate logic in the memory wrappers.

‘On the fly’ standard cell generation:

Since most of the EDA vendors are also providers of standard cell IP today, I would like to see some synergy towards creation of a system/tool where ‘on the fly’ standard cell generation would be possible.  These could be targeted towards area or power or performance. I have seen very little of this being explored by EDA companies and would like to see some serious effort in this direction in the coming year.”


 Anindya Saha is Associate VP (VLSI) at Saankhya Labs (Bangalore). Email:

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