Archive for 2013
Tuesday, May 14th, 2013
These two trend setters share their opinions on the BIG DAC themes in 2013.
I see two related trends:
1) More signoff activity earlier in the design flow
2) More focus on IP quality and usability
Both of these trends represent a maturing of design tools and business models. Because of the tremendous complexity that sub-20 nm design brings, it becomes more important to get the design right as early as possible. The tools are maturing in the earlier stages, and more designers are demanding clean reports, or sign-off level quality audits as a result. This is helping to reduce schedule delays and design costs – good for the industry.
Semiconductor IP is also maturing – both use models and business models. There is a growing focus on reporting delivered quality and robustness. This will allow IP providers that deliver the best IP to flourish. Also good for the industry. We’ll see an increase in conversations about IP providers collaborating with the rest of the ecosystem at DAC. Another good trend.
Tuesday, May 14th, 2013
DAC is upon us….and in Austin, of all places – the island in the middle of Texas.
As it’s getting closer, we were wondering what the BIG theme is for the 50th DAC. So, we asked a few of our friends and colleagues in the industry. Here’s what a few of them had to say.
I expect DAC to continue to explore low power challenges, with much talk about solving FinFET issues at 14 and 10 nm. Then there is the ever expanding SoC and how to handle all of the challenges that come with greater integration and IP reuse. Finally, what’s DAC without a discussion of Moore’s Law and whether it will/won’t continue to define industry progress in the years to come?
~ Joe Desposito, Editor-in-Chief, Electronic Design
Tuesday, April 2nd, 2013
Cary Chin, Director of Technical Marketing at Synopsys, has an intriguing take on how to approach verification now that the mandate for design project managers is to meet the low power requirement of the target end-product. Chin says that if we look at verification in terms of fine and broad “granularity,” users will meet their verification goals with a lot less angst and anguish. However, at first glance, I had no idea what Chin was talking about…which is why we asked him to join us and talk about this idea.
Ed: Cary, you’ve been recently talking about granularity in verification, especially in terms of low power. What does this all mean?
Cary: When I think of granularity in low power design, I’m thinking about the size of the “chunks” that we manipulate to improve the energy efficiency (or “low power performance”) of a design. For example, in most of today’s low power methodologies, large functional blocks are the boundaries we work within – we can shut down these blocks or manipulate the voltage to save energy when peak performance isn’t required. This boundary level isn’t just a matter of convenience; our tools and methodologies for both implementation and verification can only deal with certain levels of complexity, so we are confined in many dimensions in how we can pursue finer granularity.
Monday, March 4th, 2013
In a casual conversational exchange I overheard last week at DVCon (which reminded me of what Steve Jobs said to John Scully – “Do you want to sell sugared water for the rest of your life or do you want to…change the world?” – someone asked if the other’s company wanted to dink out press releases forever or if the company wanted to tell a story that mattered to its audiences.
This conversation got me thinking……There’s nothing wrong with sending out press releases but companies get optimal effect and value when they issue press releases for more than mere information distribution.
What would that be? To reinforce, substantiate or bolster the company’s story. Sending out press releases (or saying, writing or doing any outbound efforts) ought to convey at least one of the company’s message points.
Monday, February 25th, 2013
So you thought our blog last week was our last prediction? Just kidding.
We actually have one more prophesy……from Michel Courtoy, esteemed EDA executive, entrepreneur and angel investor.
“As a member of the EDA community, when I look at 2013, I see a key dynamic in our customer base: chip = SoC. Across the board now, designs are created by combining multiple IPs from different sources that include embedded processors, multiple interfaces and memories. This is true across the spectrum from simple microcontrollers, to multi-function chips for consumer devices, all the way to the most complex multi-core microprocessors. Hence technologies that accelerate the design and verification of SoCs will thrive while technologies targeting the IP-level will find a saturated market.
Internal to the EDA market, we have been bombarded with messages of gloom triggered by the consolidation that has eliminated most ‘mid-size’ EDA suppliers, leaving mainly the ‘Big 3 and the 100 dwarfs’. Well, this might be the opportunity that the start-ups need: where will the Big 3 fill their shopping cart now when looking for new technologies? To stay competitive, the Big 3 have to go back to acquiring start-ups and find a way to monetize new technologies in their sales channel. This will reinvigorate the ecosystem for EDA start-ups and lead to more innovation.
Tuesday, February 19th, 2013
Our final prediction for 2013 comes from Mike Gianfagna, VP of Corporate Marketing at Atrenta, and prognosticator extraordinaire:
“By the end of 2013, the names of the Big 3 EDA companies will not be the same as they are today.”
Monday, February 11th, 2013
Today’s prediction comes from Ravi Ravikumar, Vice President of Marketing at ICScape Inc. Ravi, who has over 18 years of experience in marketing, business development & project/program management in the EDA and semiconductor industries, gives his two cents on timing and power closure for 2013…..
“If you think timing and power closure were difficult issues at 40 and 28nm, they are going to get worse at 20nm. The traditional means of addressing timing/power closure as a post-implementation step using custom scripts that call on sign-off STA and physical implementation tools to achieve closure is taking too many iterations at 28nm.
As geometries reduce below 28nm, timing/power are more difficult to close due to design-related complex physical requirements, process and manufacturability issues like double/triple patterning and VT cell spacing rules create more R/C effects, impacting timing and power. Power issues in-turn lead to temperature and reliability problems. Design closure becomes a multi-dimensional task.