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Archive for 2012

Powering up at DAC with Atrenta’s Kiran Vittal

Thursday, May 31st, 2012

 

I recently talked with Atrenta’s senior director of product marketing, Kiran Vittal, about power management/optimization trends and approaches that we’ll see at DAC next week.

Ed: So power, or rather more rigorous power management will be a hot topic at DAC. How come? What will be different this year?

Kiran: As we all know, power is of the biggest concern to both mobile applications as well as wired devices. An average mobile SoC is over 100M gates operating at over 500Mhz and designers do everything necessary to apply all known power management techniques to reduce power.

It will also be interesting to see that application processors for cloud-based servers are now being designed with over 10 power domains to shut off power in non operating regions and a quad core SoC consumes around 5 watts during maximum utilization and as little as 0.5 watts during idle time.

Ed: So what approaches are we going to hear about @ DAC?

Kiran: We are going to hear about power management, power intent creation using standards, power optimization, power verification and sign off.

Ed: How do they stack up?

Kiran: It is very clear that any power management and optimization technique applied at the gate level is too late to make any difference to the aggressive low power requirements. Early power planning, RTL power estimation, automated reduction around both registers and memories and early power intent verification is the only way to achieve today’s aggressive power goals for both mobile as well as wired chips.

Stop by Atrenta’s booth (#2230) to talk about Kiran’s views with him!
……………..

 

Note: Lee PR does work for Atrenta

ICScape got $28M funding, exhibits for first time at DAC

Friday, May 25th, 2012

 

Named by industry observers as “the biggest EDA company you’ve never heard of” and “a rare and endangered species” of EDA companies, ICScape will bolt out of stealth mode to exhibit at DAC for the first time.

Founded in 2005 by Steve Yang and Jason Xing, the company’s been busy over the last year.  How?  Merging with analog EDA vendor Huada Empyrean Software (HES), getting that US$28M infusion to fund global R&D, customer support and sales expansion, and working on OpenAccess-based product lines that we’ll probably see in some integrated form toward the end of 2012.

ICScape’s booth will greet attendees right at the entrance to the exhibit floor, in Booth 1602.   The company’s executives will be there to:

1)  talk about its technology,

2)  introduce current customers (a major silicon valley Fabless IC company and a major Silicon Valley analog device company) who will also be available at the booth to share firsthand experience,…..and

3)  ensure that ICScape will be one of the EDA names that all of you will have heard of.

See what Paul McLellan,  Mike Demler and  Brian Bailey have to say about ICScape:

http://www.semiwiki.com/forum/content/1248-biggest-eda-company-you-ve-never-heard.html

http://www.eedailynews.com/2012/05/examining-rare-and-endangered-species.html

http://www.eetimes.com/electronics-blogs/other/4372423/New-Companies-exhibiting-at-DAC—ICScape

See you at DAC!

 

——————-

Note:  Lee PR does work for ICScape.

Atrenta’s unified platform

Tuesday, May 15th, 2012

Maybe Atrenta is saying goodbye to the thought-bubble guy…..

Atrenta’s SpyGlass has always been the dominant name in the company’s brand portfolio,and for good reason. It’s the dominant product in RTL design analysis, verification and optimization.

Now, Atrenta is reconfiguring its product lineup to formalize this state of affairs. SpyGlass now becomes the unifying platform for all Atrenta products.  Sort of the mother ship that all Atrenta products are based on.

So what’s a unified platform? All the tools now share a common set up and debugging methodology and tighter GUI. And what can users verify and optimize from this new unified platform? Syntax, power, testability, clock synchronization, timing and routing congestion. All at the RTL stage, well before detailed implementation begins.

(more…)

Karen Bartleson’s trek

Thursday, April 12th, 2012

Take a look at Karen Bartleson’s interview here!

http://www.eeweb.com/pulse/issue-41-2012

While we all know Karen as the standards guru at Synopsys, her story on how she got here – and next year, to the Presidency of the IEEE Standards Association – speaks to her resolve, smarts and diplomacy.

Interestingly, her engineering education experience speaks to San Jose State engineering dean Dr. Belle Wei’s thoughts on women in engineering. That “back in the day” (which is another way of saying no years allowed here) women engineering majors peaked in number, and have fallen since.

Seems to me that it’d be a fascinating interview: Bartleson and Wei on this topic…why it’s dropped and what to do about it.

One suggestion on the article: EEWeb could have included a picture of Karen’s yellow Camaro. Maybe she’ll drive it to DAC this year!     You’ll know that Karen is a-coming when you see the car in the pictures below.

3D in Monterey Next Week

Thursday, March 29th, 2012

 

This event is happening next week! Worth signing up if you can get down
there!………

 

EDPS is coming up again!  It’ll be held April 5-6, 2012 at the Monterey Beach Hotel in Monterey California.

This year, the 3D topic will be the focus of day two.

First and foremost,  Riko Radojcic, director of engineering at Qualcomm, will be talking about the 3D IC roadmap as the keynote speaker on day two.   (see his views on 3D standards:  http://www10.edacafe.com/blogs/ed-lee/2011/04/11/riko-radojcic-on-3d-standards/

Following the 1-hour keynote will be four 1/2 hour talks on various specific 3D-related topics:

* Stephen Pateras of Mentor on BIST for 3D ICs

* Arif Rahman of Altera on FPGA design challenges, presumably 3D ones

* Marc Greenberg of Cadence on the wide-IO standard for putting memory stacks on processors

* Sandeep Goel of TSMC and Bassilios Petrakis of Cadence on an end-to-end test flow for 3D IC stacks

Then there’s a lunch panel on 3D, moderated by Steve Leibson of Cadence,  with these panelists addressing: The short-, medium and long-term path to the 3D Ecosystem.

* Herb Reiter

* Samta Bansal of Cadence

* Dusan Petranovic of Mentor

* Deepak Sekar of Monolithic 3D

* Steve Smith of Synopsys

* Phil Marcoux of PPM Associates

Herb is arguably the primary 3D observer and advocate on what technologies have to be in place to handle the upcoming 3D challenge that’s starting to hit designers now.

John Swan is the General Chair of EDPS 2012. Herb Reiter is the Session Chair for the keynote, four shorter presentations and the panel discussion during  “3D Day”, Friday, April 6.

Very worthwhile to attend if you can get the time off.

Turning the tables on Graham Bell

Tuesday, March 27th, 2012

 

All of us in EDA know and know of Graham Bell, head honcho of EDA Café and notorious video chronicler of EDA. Liz and I often wonder, “who hasn’t Graham interviewed on video?”

Well, we were able to grab the microphone (after a little jostling for the mike) and camera and ask Graham what he thought was happening in EDA and with EDA media these days.

Here’s what he had to say.

3D in Monterey

Thursday, March 22nd, 2012

EDPS is coming up again!  It’ll be held April 5-6, 2012 at the Monterey Beach Hotel in Monterey California.

This year, the 3D topic will be the focus of day two.

First and foremost,  Riko Radojcic, director of engineering at Qualcomm, will be talking about the 3D IC roadmap as the keynote speaker on day two.   (see his views on 3D standards:  http://www10.edacafe.com/blogs/ed-lee/2011/04/11/riko-radojcic-on-3d-standards/

Following the 1-hour keynote will be four 1/2 hour talks on various specific 3D-related topics:

* Stephen Pateras of Mentor on BIST for 3D ICs

* Arif Rahman of Altera on FPGA design challenges, presumably 3D ones

* Marc Greenberg of Cadence on the wide-IO standard for putting memory stacks on processors

* Sandeep Goel of TSMC and Bassilios Petrakis of Cadence on an end-to-end test flow for 3D IC stacks

Then there’s a lunch panel on 3D, moderated by Steve Leibson of Cadence,  with these panelists addressing: The short-, medium and long-term path to the 3D Ecosystem.

* Herb Reiter

* Samta Bansal of Cadence

* Dusan Petranovic of Mentor

* Deepak Sekar of Monolithic 3D

* Steve Smith of Synopsys

* Phil Marcoux of PPM Associates

Herb is arguably the primary 3D observer and advocate on what technologies have to be in place to handle the upcoming 3D challenge that’s starting to hit designers now.

John Swan is the General Chair of EDPS 2012. Herb Reiter is the Session Chair for the keynote, four shorter presentations and the panel discussion during  “3D Day”, Friday, April 6.

Very worthwhile to attend if you can get the time off.

Predictions 2012 – Persistence of Memory

Thursday, February 9th, 2012

To finish off our series of predictions, I would like to point you to another series of interesting and informative prophesies.  Click on the following topics to see these predictions collected by Brian Bailey, Editor of EDA DesignLine.

Industry Trends

Tools

ESL

IP and Physical Design

The Bold Prediction for EDA

 

A big THANK YOU from Ed & me (Liz) to all who shared their eye opening predictions with us.  Click on their names to see their predictions.  Mike Gianfagna, Karen Bartleson, Paul McLellan, Jens Andersen, Bob Smith, Steve Schulz, Mathias Silvant, Herb Reiter, Max Maxfield, Chris Edwards, John Barr.

 

Only time will tell……

 

The Persistence of Memory, 1931, Salvador Dali

 

Predictions 2012 – Barr on Big…Semi, Foundry, EDA

Wednesday, February 1st, 2012

In 2012, we’ll see tablets and smartphones changing the world.  That’s another way of saying Apple’s moves will have huge implications in semiconductors, foundries and EDA.

Apple’s use of the Samsung foundry has started an arms race between Samsung, TSMC and Global Foundries.  Samsung is ramping up to meet the capabilities and capacity of TSMC.  Intel is being pushed to stay ahead technologically and to consider new business models. Global Foundries continues to work to ramp its yields.

This situation will be good for semiconductor equipment and EDA vendors as well.  Their tools will facilitate the new processes and the link between design and manufacturing.

Another element: in 2012, we’ll see the supply chain continue to consolidate. Why?  The cost to design a complex SoC requires a big budget and a big market opportunity.  Only the largest of semiconductor companies can tackle these designs.  This increasing cost helps the FPGA vendors.

The foundries face increasing technology and capital requirements to move to new process nodes.  Only a few will make it.

The public markets have been closed to EDA companies for a number of years making acquisition the most likely exit for EDA startups.  Apache chose to be acquired by Ansys in 2011.  It has been difficult for a new, large EDA competitor to emerge.  This bodes well for Big EDA in its negotiations with Big Foundry and Big Semiconductor.  In 2012 I believe there are several EDA companies poised to go public.

Who will be the beneficiary of these changes in 2012?  Apple.  Consumers should also benefit as new, leading edge fab capacity will be used to make exciting new devices.

John Barr
Portfolio Manager
Needham Aggressive Growth Fund
Needham Growth Fund

445 Park Avenue
New York, NY  10022
(212) 705-0462

 

Predictions 2012 – Double Patterning in Litho

Monday, January 30th, 2012

The main technical breakthroughs we can expect this year will probably revolve around double patterning in lithography as EDA companies try to optimize the technique for density and performance. And it will probably have knock-on effects way up in the design flow, forcing designers to adopt much more regular designs. But, unless EUV sees a major breakthrough, double and further levels of multiple patterning is something people will need to get used to.

Regularity is likely to become a feature of low-power design as well. Although it hurts effective density, the drive to cut power consumption will see much more use made of on-chip redundancy – we’ve already seen some of that in the nVidia Tegra 3 and the ARM Big.Little initiative. We could see those techniques begin to extend into ultralow power circuits using near or subthreshold devices as engineers discover how to model circuits effectively and recover lost performance at very low voltages.  Some of these techniques will also help reinvigorate older processes – using better EDA to trim power consumption instead of relying primarily on process changes to deliver better energy efficiency.

Chris Edwards
Technology writer: Engineering & TechnologyNew ElectronicsLow-Power Design BlogTech Design Forums

 

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