Industry pressure is growing to deliver more mainstream 2.5D and 3D stacked die semiconductor products within the next 1-2 years, driven by the need to improve I/O bandwidth, reduce power consumption, and optimized choice of process technologies for different portions of a complex SoC. It is therefore quite possible that 2012 will see one of the large mainline EDA vendors broadly announce a full “platform” product suite targeting the design of 2.5D and 3D stacked die making use of through-silicon-vias (TSV’s). This design platform would likely incorporate tools from value-added niche vendors, and be endorsed in a large foundry reference flow. Open standards will later expand the range of choice and interoperability over time.
President and CEO