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Archive for March, 2011

What if….no more big three?

Monday, March 28th, 2011

Continuing with my conversation with Tom Kozas, president of CADmazing Solutions, I asked him about a hypothetical scenario:

 

Ed:   So Tom, what would happen if for some reason, the big three EDA vendors all went away?   So instead of Cadence, Mentor, Synopsys,  the biggest three would be Magma, Apache?  Atrenta?

Tom:  I think this raises even more questions.

Ed:  Hmmm…interesting.  What questions?

Tom:   Several come to mind:  Would this mean renewed growth for the industry? Would the fundamentals change that encourage investment in new startups? Would the design flows become more or less integrated, collaborative, and global?

Ed:  Ok, good questions to ponder.   So what would be THE big issue?

Tom:  The “Silicon” in Silicon Valley is missing.  Without investment in new semiconductor startups, growth simply won’t happen.  Virtually all new design starts are happening within the big systems and semiconductor companies which means the only way to grow an EDA company, is to steal market share.

But would this translate to increased value for the remaining EDA companies in the eyes of the financial community?  What’s interesting about this hypothetical is, even though it would put the remaining EDA companies in a position to take advantage of this opportunity they might not be able to.

Ed:  Just to play devil’s advocate, why wouldn’t that next set of players, whoever they are, be able to take advantage of the sudden disappearance of the big three?    And who do you consider to be that next set of players?

Tom:  Good questions.   But let me respond by saying what they will need to provide.

So, the next big three will have products that have great user interfaces, provide online collaboration, and be part of a new ecosystem that enables innovation.  The industry already has advanced technology but needs graphical and command-line interfaces that exploit the online design environment.

Second, designers don’t necessarily sit in the same building but often have to work on the same problem. For example, two or more designers should be able to share the timing database and bring up the same timing path without having to rerun static timing analysis and do it within minutes no matter where they are in the world.

Finally, the current EDA ecosystem is in the dark ages, there needs to be a new model that facilitates new algorithm and tool development with a reward system.

Ed:  Tom, thanks again for your insights.

 

Three Shifts for SIP

Tuesday, March 22nd, 2011

Ken Brock is the Product Marketing Manager for DesignWare Logic Libraries at Synopsys.  Ken shared with us here his view of the trends he sees for the future of semiconductor IP.

 

What Does the Future Hold for Semiconductor IP?

The marketplace for semiconductor IP (SIP) continues to grow at double digit rates. According to Gartner Dataquest, the number of third-party semiconductor design IP blocks in an average chip design will double from the current level and the SIP market will reach $2.3B in 2014. IBS and Semico believe the SIP market will be greater than $3 billion in 2014.

We see six major trends in IP:

  • Convergence: The increased demand for “Smart” consumer electronics is driving more features and functionality into a single device such as the latest craze in tablets shown at this year’s Consumer Electronics Show (CES). This trend is causing significant changes in SoC designs in areas such as power and performance requirements that drive technology node migrations, and in increased clock frequencies to keep up with bandwidth needs.
  • Core versus Context: Does this function differentiate the SoC? Interfaces like PCI Express® and USB have to work but they don’t generally differentiate the SoC.  As an IP vendor, we see many different applications spaces for our IP and we have to ensure that IP works over a broad range of configurations and products.
  • Fab-outsourcing: More outsourcing of manufacturing means more opportunity for customers to use off-the-shelf IP to meet their design requirements, and more demand for IP vendors to create high-quality IP on the most advanced process nodes.
  • Power, Performance, Area: As many semiconductor designs compete for the key sockets, having the fastest performance, lowest power and smallest area is often a key differentiator of the design with respect to processor performance, battery life, packaging cost and silicon cost. Choices of foundation IP (memory and logic) providers make a big difference between winners and also-rans.
  • Consumer-driven schedules: Shorter time-to-market and more features means that designers need to de-risk schedules by using high-quality IP solutions that have been proven time and time again in the market place.
  • Expense control: It is often less expensive for companies to buy third-party IP than to develop it themselves. This is particularly true in advanced nodes where the complexity of IP development increases rapidly with increasing data rates, restricted design rules and increasing variability. As an example, our estimate is that a 28nm standard cell and memory IP platform is at least five to 10 times as complex to design and verify as compared to a similar platform at 40nm.

With these trends as the backdrop, we see significant shifts in the SIP market as it continues to evolve during the next five years:

  • Most SoCs will have about 70 to 80 percent of their functionality in reused IP (internal and/or 3rd party). The majority of these IP blocks will be memories with thousands of instances per chip all connected with a variety of standard cell configurations. Optimized standard cells and memories can significantly impact the performance, power and area of a SoC.
  • Individual IP products will yield to more complex IP subsystems. These subsystems will include application-specific blocks and software. IP integration services will become increasingly important to validate the IP in the system context.
  • Multi-core designs will drive increasingly complex architectures. A virtual prototype of the IP and the larger SoC will enable earlier and more efficient development of application software and middleware.

This is a pivotal time for the semiconductor IP industry as companies strive to develop the best solutions to help designers accelerate their time from concept to implementation. These solutions generate value throughout the design chain by accelerating hardware/software integration and systems validation, allowing efficient SoC architecture exploration and optimization, creating and optimizing functional blocks, and using high-quality semiconductor IP. Designers are turning to trusted third-party SIP solutions to help integrate advanced functionality with the least amount of risk. Winners will choose wisely.

 

Tom Kozas on EDA in the Clouds

Tuesday, March 8th, 2011

I recently grabbed coffee with Tom Kozas, President of Cadmazing Solutions. Since Tom’s staff works with a variety of domestic and international electronic designers spanning many industries, he sees a lot of different attitudes toward design tools. So I asked him:

Ed: So Tom, what about EDA in the clouds? Do your clients see that as desirable? Even viable?

Tom: It all depends on who is realizing the value.

Ed: When you say “realizing the value,” what do you mean?

Tom: OK, good point. EDA vendors have a completely different reality of their product value than do their customers. The EDA vendors believe that their product provides “absolute” value while EDA customers only see incremental product value. At CADmazing we deal with this reality with every customer and vendor we engage with.

Ed: Why the vast discrepancy?

Tom: Well, it’s the customer that commits the extra time and effort to go from incremental to absolute value for the complete design flow. As for EDA in the cloud it won’t fix the EDA industry.

Ed: No? Why is that?

Tom: Large customers already have their own clouds accessed through virtual private networks. So if a customer’s design environment included tools from each of the three top vendors, would this mean they would have to log into three different clouds?

Ed: Well, would the EDA customers then create their own cloud interface that all EDA tools would have to work? Or that the big three could create a standard cloud interface?

Tom: I just don’t see this type of collaboration happening among the top three EDA vendors. The industry would need something like an “Open Cloud” initiative that enables customers to have access to any EDA tool they want, especially from EDA startups – once the world comes back to its senses and starts funding them again.

Ed: So what’s your take on when EDA will be in the cloud?

Tom: Some EDA companies are already offering their products on the cloud. EDA companies will need to be careful that they are not creating a solution looking for a problem.

If EDA vendors want to successfully offer their tools and services on the cloud, they will need to provide an advantage that increases their customers’ business success. A technical and/or business advantage that goes way beyond outsourcing compute cycles.

Ed: Tom, thanks for your take on the EDA cloud.
………………………………..

Tom Kozas is President and principal consultant of Cadmazing Solutions www.cadmazing.com and has worked for years in engineering and marketing at EDA startups – such as Monterey – and established companies – such as Hughes Aircraft, Cadence, Compass. Cadmazing provides IC CAD development & implementation services for analog, digital, and mixed-signal system-on-a-chip (SoC) technology and full-custom designs. Tom’s email is: tomk@Cadmazing.com.

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