Ed LeeEd Lee has been around EDA since before it was called EDA. He cut his teeth doing Public Relations with Valid, Cadence, Mentor, ECAD, VLSI, AMI and a host of others. And he has introduced more than three dozen EDA startups, ranging from the first commercial IP company to the latest statistical timing analysis characterization company. Ed brings his knowledge of the history of the industry, the companies, the executives, the products, the editors, the analysts, the market researchers, and the investors. And crucially, he knows the trends and issues. « Less
Ed LeeEd Lee has been around EDA since before it was called EDA. He cut his teeth doing Public Relations with Valid, Cadence, Mentor, ECAD, VLSI, AMI and a host of others. And he has introduced more than three dozen EDA startups, ranging from the first commercial IP company to the latest statistical … More »
March 1st, 2010 by Ed Lee
Steve Leibson in Leibson’s Law did a comprehensive and insightful job of covering the Hogan/McLellan entrepreneurial workshop in his blog on Wednesday. Thank you, Steve! And thank you, Jim and Paul, for enlightening us on how to start up an EDA company.
Jim and Paul made some very hard-hitting points in this valuable how-to workshop (at DVCon Tuesday night), one of which was emphasized by Leibson: “Sizzle is the highest leverage marketing point” said Hogan.
Afterward, a couple of attendees shared with us that “there is no sizzle in EDA!” And “as we all know, many engineering driven startups (even some engineering driven mature companies) undervalue or don’t understand the importance of sizzle - a big mistake.”
What is sizzle? How do you define it?
Is there sizzle in EDA? Why or why not? Who has it, if there is sizzle in EDA?
Let us know what you think……
~Liz Massingill
Tags: DVCon, EDA, Jim Hogan, Lee PR, Leibson's Law, Paul McLellan, startup, Steve Leibson 5 Comments »
February 5th, 2010 by Ed Lee
 Jim Hogan
 Paul McLellan
Contrary to what we read last year, EDA is not dying…
In fact, there are areas of high growth and lucrative start up opportunities in the decade ahead.
Who says so? EDA and IP investor Jim Hogan and start up CEO Paul McLellan.
Take a look at this upcoming interactive workshop to be given by Jim and Paul at DVCon.
To register contact me at liz@leepr.com. (see details below) — Liz
So you want to start up an EDA company? Here’s how…
An interactive workshop with angel investor Jim Hogan and start up executive Paul McLellan
Dire predictions about the death, stagnation or maturation of EDA are premature, says noted angel investor Jim Hogan, a major shaper and influencer of the EDA industry. He and cohort Paul McLellan actually see lucrative opportunities in EDA. Startup founders just need to see end-product design trends and find problems to solve that’ll appear in the next 18-24 months.
Come to this workshop and hear how to get a startup going in EDA. Get Jim and Paul’s take on what areas in EDA and IP are potentially successful – and those areas that won’t yield a reasonable return on your efforts.
Talk to Jim and Paul about the process of starting up an EDA company – what the angel investment process is, what to expect, how to figure out your exit strategy.
When?
Tuesday
February 23, 2010
6:30 – 7:30 pm
@ DVCon (DVCon registration not required)
Where?
DoubleTree Hotel
Oak Ballroom
2050 Gateway Place
San Jose, CA 95110
1-408-453-4000
RSVP to:
Liz Massingill
liz@leepr.com
3 Comments »
February 1st, 2010 by Ed Lee
(As we all know, Richard Goering is a longtime EDA editor who went to work for Cadence in March 2009, where he writes the Industry Insights blog and works on various writing projects. I recently had a chance to talk with Richard about his year on the corporate side of editorial writing and the state of EDA editorial: where it’s going and what it’ll look like, if it continue to exist. It will, but…BTW, something’s different about Richard’s photo…)

ED: It’s been about a year since you moved from editorial over to Cadence. What differences, if any, do you see?
RICHARD: First, there’s a difference between blogging and news reporting. A blog is shorter and more personal, and is written in a different style. After many years of conventional news reporting, blogging has taken some adjustment.
Also, writing a corporate-sponsored blog is different from writing for an independent publication that covers news from all vendors. With the Cadence Industry Insights blog , I’m writing about most of the same issues I would have covered for EE Times, but where appropriate I’ll include a Cadence perspective or product mention. I don’t generally write about developments from other companies, unless some sort of Cadence partnership is involved. I should note, however, that since I’m focusing on issues rather than products, I don’t often write blogs about new Cadence products.
ED: So it’s been a change to come over to the dark side…not that there’s much of a “light side” any more, huh? What did you perceive as the dark side and what does it look like now, to you?
RICHARD: I don’t really think of it in terms of a “dark side” and a “light side.” Independent publishers are not doing charity work – they’re in business to make money like everyone else, even if they don’t succeed!
For me, working for a major EDA company has certainly been an educational experience. I now have a much better idea of how EDA companies function. Before EDA companies were mysterious monolithic entities that spit out press releases and products. Now I see the “people” side of the industry – lots of creative and diverse people who have many different ideas, and somehow come together with a consistent message.
ED: You’ve covered EDA for over 20 years. Clearly the publication world has changed, is collapsing as we speak. What lies ahead for EDA publications and coverage?
RICHARD: A lot less coverage, as we’ve seen already. Still, publications like EE Times, EDN, Chip Design Magazine and Electronic Design do have some EDA coverage. But a lot of the coverage going forward will come from blogs, forums, and various social media outlets.
ED: Where EE Times is concerned, it seems that there has to be some connection with a chip design issue for there to be EDA coverage. Otherwise, it goes to EDA Design Line. I think that’s fine, but it sure says something about how that once-mighty publication has changed, huh? Well, don’t let me put words into your mouth. How is the change in EE Times emblematic of what’s happened to EDA editorial?
RICHARD: It’s not just EDA editorial – EE Times has a lot less editorial, period. There is still some EDA reporting once in a while, but there seems to be more of a semiconductor focus. That probably makes sense given the lack of EDA advertising and the greatly-reduced editorial resources.
ED: What role will the new era bloggers (indie, corporate, editorial, PR) play? How will those roles evolve?
RICHARD: Blogging provides a new information channel that’s hopefully written in an engaging style, by someone with expertise in a given area. Given that some EDA bloggers are chip designers or consultants, it can be a “peer to peer” communications channel. It can also be a two-way channel if a conversation develops.
Independent bloggers, I suppose, are those who are not paid by a company to blog, although many do have employers. While every blogger has her or his own biases and points of view – a point of view, after all, is what blogging is all about – independent bloggers have the potential to be on neutral ground with respect to EDA vendors.
Corporate bloggers will reflect the positioning of their companies, but they can also provide a good deal of useful, in-depth information that you won’t find elsewhere. With Industry Insights, I have been able to write some “inside look” kinds of blogs that it would have been difficult to write from the outside. For example, I wrote a series of blogs about what it takes to port EDA software to multicore platforms, drawing upon Cadence’s experiences in this area.
Due to the lack of editors, there are very few EDA editorial blogs. Those that exist are picking up some of the coverage that’s missing from the electronics trade press. An example is Ron Wilson’s Practical Chip Design. I haven’t seen much in the way of blogs from PR people, although yours is an exception.
ED: OK, since you bring it up, what role do EDA PR bloggers have in EDA blogging?
RICHARD: I think PR bloggers would do best to focus on issues like social media, PR, and advertising, as opposed to technology. With all the changes in the media, there’s plenty to write about.
ED: But blogging seems more opinionated than EDA editorial, which you covered for so long and so rigorously. I mean, clients were intimidated by the perceived “wrath of Goering” and would oftentimes minimize their hype when being interviewed by you. Thus, we got a comprehensive and objective overview of the technology area from you, even when you covered new products. Will we see objective reporting disappear?
RICHARD: No. As I noted, there is still some EDA reporting in the traditional media, and some bloggers do objective evaluations of major new products and announcements. But the days when every EDA announcement would receive coverage are long gone.
ED: So what role will traditional press play?
RICHARD: I think there will be some continuing coverage of really big announcements or developments. But there will be a lot less product coverage and new company coverage than there used to be. Unfortunately, there are a lot of press release rewrites in the press these days. That doesn’t provide much useful information for the readers.
ED: How possible is it that an EDA press disappear? Why?
RICHARD: Very simple – lack of advertising. It’s part of the meltdown we’re seeing across the publishing world. Also, EDA stories don’t get tens of thousands of readers. There’s a very small, specialized audience, although they have big wallets.
ED: What’s there to keep EDA honest if there’s no longer an “industry press?”
RICHARD: There is an industry press – there’s just less of it. There are also a growing number of bloggers watching EDA developments. But more and more it will be up to the users to help keep EDA vendors on the right track. With the ability to start a blog or comment on blogs, join on-line forums, speak at user group conferences, and participate in Twitter groups like #EDA, EDA users now have a voice – and they will hopefully use it for the betterment of the industry.
ED: What’s your sense of pay for play in editorial? Good, bad or necessary?
RICHARD: I’m not going to say it’s bad, but if a company pays to have an article written, I think that should be made clear to the reader.
ED: Well, EDA’s benefited from your historic participation in the industry. Witness your DAC award a few years back. It’s been, what, over 20 years, starting at Computer Design? I’m not sure anyone can see an EDA industry without Richard Goering in place. Thanks for taking the time to catch up.
RICHARD: And thank you for the opportunity! After interviewing your clients for years, it’s an interesting turn of events to have you interview me.
– end –
Tags: blogging, Cadence, Chip Design, EDA, EDA bloggers, EDA Design Line, EDN, EE Times, Electronic Design, Industry Insights, Lee PR, Practical Chip Design, Richard Goering, Ron Wilson 4 Comments »
January 25th, 2010 by Ed Lee
(I had a chance to sit down with Piyush Sancheti, senior director of Business Development at Atrenta as a follow up to a brief conversation on how design teams could measure – and indeed, recognize – quality in design.)
 Piyush Sancheti, Atrenta
Ed: It’s good to sit down with you, since you mentioned “quality design” the last time we talked. You remember that I couldn’t quite grab hold of the concept in my head as something that can be tangible, which is when we decided to talk again.
So let me ask the big question: just what is “design quality? And what is “design quality closure?”
Piyush: Good questions, Ed. Design quality means many things to many people.
In my view, there are two major classes of quality - 1) is the design or IP going to meet its functional requirements and adhere to the protocol or spec it was intended for 2) is the IP going to successfully integrate into the chip or sub-system it is was designed for, and if that chip is going to meet it’s requirements and successfully implement in silicon. Meeting both these quality requirements and achieving the target goals of the chip is what I would call design quality closure.
Ed: So there is a tangible metric when you talk about quality design. How do you measure that quality…by the percentage of functionality the designer is able to integrate? I guess I’m asking: how do we put a number on quality in design?
Piyush: Yes there are tangible metrics for design quality as it pertains to functional quality (item 1 in my definition of quality). For IP like processors, bus fabrics, USB, PCIX, SATA, etc. there are well defined specs and benchmarks that are used as measures of quality. However, there aren’t well defined quality metrics for integration or implementation readiness of an IP.
These have to do with meeting the requirements for area, power, timing, clocking of a design. These quality criteria are often overlooked during the architecture and RTL phases of the design, and tackled much later during the implementation phases as design gets closer to tapeout and silicon. Efforts have been made in the industry to define IP/design quality standards for implementation and integration, specifically the IEEE QIP standard. While these standards are important, enforcement of such standards continues to be a challenge. A methodology and tools are a way to enforce design quality standards, and this is an area of focus for Atrenta.
Ed: OK, got it. So we need to look at the target performance and how close the designer gets, which is somewhat subjective, it seems. But designing quality in has to have a cost, right? Probably not in chip performance, since you have goals there you have to meet. But in designer productivity, maybe? For instance, guardbanding could be seen as a quality technique implementation, and who wants excessive guardbanding? I mean, that’s a little exaggerated but …
Piyush: Yes, nothing is for free! But one can argue that design quality and designer productivity go hand-in-hand. The cost of design is sky rocketing, so you want to build your key IPs once and reuse them many times over. Effective design reuse is a surefire way to boost productivity.
You may need to put some additional effort to design your IP “Right from the Start”, as we say at Atrenta, and enforce the quality measures. But the payoff is in the reuse of the IP over multiple designs, products or market segments, and not having to burn engineering cycles fixing the same issues over again.
Ed: Ok, got it. Now I recall you saying that somehow, the concept of platforms enters into the discussion here. How so?
Piyush: The concept of platform-based design is based on building high-quality IPs and performing rapid chip assembly to meet the needs of multiple customers or multiple market segments. In my view, the productivity gains in chip assembly and integration far outweigh the additional effort required in higher quality standards for your IP.
Ed: OK…so quality equals productivity gains? So if you’re a design team manager on a project and your team is designing new IP, how do you figure out how to trade off quality for productivity? You have a schedule to meet. At what point do you compromise?
Piyush: It’s simple - pay me now or pay me later. If key IPs in your design are poorly designed, you have a few nasty surprises waiting for you at the late stages of your design. Your chip most likely will run into critical design closure issues whether it be die size, performance, power, clocking, and the list goes on and on. Worse even, you might get silicon back that is not working, the ultimate nightmare for a design team. As a design manager, what you need the most is predictability of results and meeting your tapeout schedule. If you have a structured methodology for managing all aspects of your design from architecture definition, to IP creation, chip integration, etc. and along the way you have objective quality criteria that can be measured and enforced, you can manage your schedule and design risk much more effectively instead of trying to attempt multiple diving catches at the tail end of your design cycle.
Ed: So it’s really not about using this or that point tool, but using a quality design flow?
Piyush: It truly is about having a structured methodology and flow with tools providing the measurement and automation.
Quality is not something you can retrofit into a design flow. What you need is a methodology to manage your design quality at each stage of the design evolution starting from spec to architecture to RTL and all the way down to silicon. Here at Atrenta we are focused on the spec to RTL aspects of design quality closure. With an increased focus on the early stages of your design, you can achieve significant productivity gains in your overall design flow. When you’re building a house, it’s a lot easier to move a wall on the drawing board, than it is to it on the job-site. And that’s what we bring to the table.
Ed: Now I understand that you’re going to talk about quality and productivity at DesignCon? When and where is that?
Piyush: Yes indeed, I am participating in a panel at DesignCon on Wed. Feb 3 2010, 3:45PM at the Santa Clara Convention Center.
The panel, which includes experts from design, IP, standards and EDA will discuss this very topic of design quality vs. productivity. Ron Wilson from EDN is the chair and it promises to be a lively discussion on an important topic for the semiconductor industry. Click here for more on the panel.
Ed: That ought to be an interesting discussion on a timely and crucial topic. Thanks for your time, Piyush.
Piyush: Thank you Ed for your time as well.
– end –
Tags: Atrenta, design closure quality, design flow, DesignCon, EDN, IEEE QIP, IP quality, Lee PR, PCIX, Piyush Sancheti, quality metric, Ron Wilson, RTL, SATA, USB No Comments »
January 18th, 2010 by Ed Lee
2009 was a rough year for an already stagnant EDA world. Looking to 2010, Liz Massingill and I asked industry colleagues, opinion makers and friends what each of them saw as the BIG trend for 2010.
Here’s what they said.
Karen Bartleson, Blogger, The Standards Game, Synopsys
http://synopsysoc.org/thestandardsgame/
The big trend in EDA for 2010 will be the acceptance of social media as an additional means for communicating with customers, partners, and competitors.
Now that blogging is settling in as a viable source of information from media people, company experts, and independent publishers, more new media tools will come into play. Not all tools are right for everyone or every situation, so the EDA industry will explore the options and experiment with a variety of community-development activities.
LinkedIn and Facebook will offer special interest groups a place to congregate. Twitter will be tested by more people - who today are curious or skeptical - as a means of immediate, brief interaction. EDA suppliers will offer new communication channels and those that are truly value-add will thrive.
The EDA world won’t change overnight, but the trends in social media will be noticeable.
Graham Bell, Director of Sales and Marketing, EDACafe
http://www10.edacafe.com/blogs/grahambell/
The BIG trend will be that designers need ALL of the technology that EDA companies have been working on and introduced in the last 18 months.
There is a lot of design work being done at 45nm and all the established tools are running at the edge of their capabilities.
New generations of parasitic extraction, static and statistical timing analysis, and automated property verification are just some of the important technologies that will be needed by design teams.
Mike Gianfagna, Vice President, Marketing, Atrenta, Inc.
http://www.atrenta.com
In 2010, we’ll see an accelerated move to doing more design at higher levels of abstraction.
Chip complexity and the skyrocketing cost of physical design, along with the advent of 3D stacks is forcing this. Designers just won’t be able to iterate in the back end in 2010 and beyond. It’ll take too long and cost too much.
Power management, design verification, design for test and timing closure will all be “close to done” before handoff to synthesis and place & route. The traditional backend flow of IC design will become a more predictable, routine process, which will accelerate its trend toward commoditization and consolidation.
This move to higher levels of abstraction will also have implications for IP selection and chip assembly. This will compel a new genre of tools to emerge. Standards like IP-XACT will help this process to take hold. Perhaps this is what ESL will become.
Richard Goering, longtime EDA editor and currently manager of the Cadence Industry Insights blog
http://www.cadence.com/Community/blogs/ii
I think the Big EDA Trend for 2010 will be SoC integration.
There will be a renewed focus on the challenges of integrating existing IP, providing breakthrough technology for design teams to quickly and reliably
assemble complex SoCs from integration-ready IP blocks, and then run
full-chip verification including both analog and digital components.
ESL is part of this story because there’s a need to move to
transaction-level IP creation, verification and integration. Hardware/ software integration and verification and will also become part of
the drive towards SoC integration.
Harry Gries, the ASIC Guy, EDA blogger
http://theasicguy.com/
As for the EDA trend in 2010, I think that EDA companies, when they recover, will choose not to hire more sales and marketing people but will invest more in other marketing tools on the Web or using social networking strategies.
A good example is a company like Xuropa, which is actually a client of mine, under full disclosure. They help EDA companies put their tools on the Web in order to help them reduce their costs for demos, product evaluations, etc.
I think that will see a lot of interest in the upcoming year as companies look for ways to do “more with less”. User group events may also move online, just like this year’s CDNLive was a virtual event rather than a real live event. Xilinx and Avnet sponsored an X-Fest this year that was also an online event. Things are moving online fast and economics will drive that.
Grant Martin, EDA blogger
http://www.chipdesignmag.com/martins/
In 2010, we’ll see the steady progress towards usable ESL tool and methodology adoption by design groups.
The areas of greatest real ESL use are the high level synthesis of data crunching blocks used in various DSP-type applications (signal and media processing), the increasing adoption of processor/SW-centric design methods, and the increased creation and use of virtual prototype models.
(Brian Bailey and I have a new book from Springer coming out in the new year on practical ESL use methods: “ESL Models and their Application: Electronic System Level Design and Verification in Practice”. See for a summary. )
Dan Nenni, EDA blogger
http://danielnenni.com/
For EDA, 2010 will be the year of the foundry. Foundries will drive new EDA flows and business models.
The TSMC Open Initiative Platform
is but the tip of the iceberg. If EDA and IP companies do NOT join forces with the foundries and take arms against the sea of semiconductor troubles - they will continue to suffer the slings and arrows of outrageous economic misfortune.
Coby Zelnik, CEO, Sagantec North America, Inc.
http://www.sagantec.com
In 2010, we will see more designs taping out in 40nm.
In an effort to minimize risk, cost and time to market, design reuse will be
maximized; many of them will be migrations of existing 90nm and 65nm products or derivative products with minor updates and tweaks.
– end –
Tags: 3D, architectural, Coby Zelnik, Dan Nenni, EDA trends, ESL, Graham Bell, Grant Martin, Harry the ASIC Guy, high level synthesis, IP-XACT, Karen Bartleson, Mike Gianfaga, power, Richard Goering, RTL, social media, verification 7 Comments »
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