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Matthieu Wipliez
Matthieu Wipliez
Matthieu Wipliez is CTO and co-founder of the Synflow EDA start-up company. He has spent the last two years working on a new programming language called C~ ("C flow") for next-generation hardware design, and developing an IDE for that language. Matthieu writes about what he loves, like disruptive … More »

Numbers don’t lie: there is virtually no interest in high level synthesis

April 13th, 2015 by Matthieu Wipliez

I finally read enough articles about high level synthesis (HLS) that give a sense of hype that just didn’t seem to be matched by what I’ve heard. Now hype is pretty subjective, but numbers are not. For example, the High Level Synthesis group on LinkedIn only has 66 members (including myself!); compare that to the FPGA – Field Programmable Gate Array group which has 22,931 members (also including myself). If we were to suppose that HLS tools target FPGA users – which most tools (such as Vivado HLS, NEC CyberWorkbench, ImpulseC, etc.) do, and assuming that both FPGA users and HLS users have a LinkedIn account, then we might conclude from these numbers that less than 0.3% of FPGA users are interested in HLS.

These numbers are just an indication that there may be a different picture than painted by the various articles about HLS. Of course, you might argue that not everybody who’s interested in a particular technology is necessarily a member on a group about this technology on a given social network, and you would be right. However, I think we can agree that pretty much everybody who’s interested in a technology will search for it at some point. Let’s see what we can dig about search patterns regarding HLS.

The graph below is a screenshot of Google Trends that plots the searches for FPGA (red and decreasing) and the searches for high level synthesis (blue, constant at just above zero). You can verify these results yourself, here is the query I used. Note how there is not enough search volume for Google to show us geographical information about these searches.

Interestingly, this seems to match the observation that there is virtually no interest among FPGA users about HLS. Results vary ever so slightly if you look for ASIC (use the “Application-Specific Integrated Circuit” topic rather than the “asic” keyword that matches a lot of things).

But perhaps this is because high level synthesis is such a new and innovative technology that we are still at the beginning of its adoption? But how can it be, when they claim 15 of the 20 top semiconductor companies rely on HLS? Enter the Diffusion of Innovations.

Diffusion of innovations

Diffusion of innovations is a framework that explains how innovations get adopted, and what makes the difference between the succesful adoption and failed adoption of an innovation.

Diffusion time

An important metric about the diffusion of an innovation is time. For example, the eponymous book shows how corn farmers in Iowa adopted hybrid seeds in the 1930s in nine years. Switching from a variety of corn to another variety requires experimentation, so the first farmers who wanted to adopt these new seeds planted them and had to wait for corn to grow, and probably repeated that experiment for a year or two. At this point you probably wonder where I’m going with this?

Well… High level synthesis (its modern form at least) is about 25 years old. You can check for it yourself, there was a tutorial on high level synthesis at EDAC 1991. Now if farmers have adopted new seeds in 9 years, but designers haven’t adopted HLS in 25 years, there’s little chance they will…

By the way, history shows that it is not until the innovators and early adopters have adopted an innovation that the real growth starts, see Crossing the Chasm for more details on how to move from early adoption to the mainstream. Now this crowd represents 16% of the total public, so there’s room for growth from 0.3%!

So what about those 15 out of 20 top semiconductor companies?

First, it is a vendor of HLS software that claims that. This is the word used by the article I linked to above, not my own choice of word. Second, there are no numbers of how many designers in these companies actually use it in their daily lives. It has been known that some EDA companies have offered HLS licenses as part of larger deals to ease the adoption, counting these clients as adopters even if they don’t use it.

Last but not least, big companies are seldom innovators/early adopters (for reasons that should be obvious). It could be a case of authoritative adoption, in other words management decides to adopt it, even if the designers themselves do not perceive any advantage in the technology!


Please comment below! Feel free to share numbers that you may have that corroborate this post; I also welcome numbers that contradict this post, good luck finding them though! 🙂

[this post was originally posted here]

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8 Responses to “Numbers don’t lie: there is virtually no interest in high level synthesis”

  1. Graham Bell says:

    My latest blog on EDACafe covered the topic High-Level Synthesis: New Driver for RTL Verification.
    As I look at recent events such as the acquisition of the HLS company Forte by Cadence (which complemented their existing product), and the announcement by Calypto of a new 3rd generation Catapult-C HLS tool, this leads me to the conclusion that there is considerable business that needs to be served.   I am not sure whether HLS is a sweet spot for FPGA designers in general.  Perhaps it would only interest the designers for big high-end FPGAs.

    I decided to look-up the number of books on Amazon for both “high-level synthesis” and “logic synthesis”. You will be surprised to learn that the results were 2,649 and 3,128 respectively. So book publishers know something that we don’t.  There is huge interest in high-level synthesis.

    • Matthieu Wipliez says:

      Graham, Forte has been acquired after about 15 years of operation. They were still calling themselves a startup even though they were nothing like a startup anymore. Think about it this way: would they have sold if they were seeing huge adoption and revenue growth? Perhaps, but for 10x the amount (instead of between $10M and $20M). See for more details and numbers, and which agree with my claims.

      The fact that Calypto is doing a 3rd or 15th generation tool is hardly relevant, you can find information on the Internet about employees saying that the company is still hardly breaking even, even after years of operation and Mentor’s support. Again, supporting my claims. I have heard similar information about Cadence C2S by the way.

      As to thinking that HLS is more useful for huge ASIC and big FPGAs would mean that the technology needs a lot of investment. That part is true, both from a financial point of view ($400K license) and time to learn point of view. Again from something that I’ve heard, it takes two years to transform a hardware designer into a HLS “wizard” (their choice of word).

      Finally, sure there may be a lot of books, have you checked if perhaps “high-level synthesis” and “logic synthesis” both include the results of a search for “synthesis”? Regardless, HLS does interest a category of people: researchers, who also happen to write a disproportionate amount of publications and books compared to engineers. I was hearing a lot about HLS hype when I worked in academia, but a lot of disappointment when I talked to professional hardware designers. Mind you, some of them have tried all HLS tools during the past 10 years, and have been sorely bitten by the difference between expectations and reality. HLS is a tiny bubble, confined to EDA, but bubble nonetheless!

  2. Samary Baranov says:

    It is a very interesting paper. I absolutely agree with your frustration about HLS tools. Really, these tools are good only for Data path dominated systems. In real life most of the systems are Control and Data path dominated and existing HLS tool are inefficient. Maybe it’s a reason why hardware designers don’t use it.
    For a long time I worked in Logic synthesis, but during latest 6 years my main goal was High level synthesis. Our HLS tool Synthagate is based on the completely new design methodology. It is the reason why Synthagate is so efficient in the design of the Control and Data Path Intensive Systems with very complex control units containing a lot of inputs and outputs.
    Please, look at my post including “What makes Synthagate different” at the end of this post. We have many examples of designs with our tool, some of them are on our site
    We are ready to make designs with any company because we are very interested to get a feedback from different designs to improve our tool.

  3. Steve Casselman says:

    HLS addresses IP generation. The hot topic is system generation, ie programming. If you look at the Altera tools they help you pipeline the data path and plug the result into an existing control framework that is done in Verilog. This is the way to go for software programmers that want a boost in performance. Hardware designers are very conservative and extremely slow to pick up new programming paradigms. Even though Verilog was introduced in 1983 it did not become “de rigor” until after 2000.

    • Spot on: hardware designers are very conservative, yes. I’d say that performance boost is a hard sell today: between multi-core, many-core, GPU, and distributed computing (aka the magical cloud), there are plenty of other ways to get very high performance, without ever leaving the comfortable realm of software. Now when you need to combine performance with low power consumption and low latency, this is where hardware really shines. But hardware is so much more than pipelined data paths; parallelism and control are just as important, if not more. Either HLS takes software as an input, and it cannot give satisfactory results, or it takes SystemC as an input, and it cannot appeal to anybody else than senior hardware designers who are also SystemC fanboys (or who are force fed SystemC, depending on management), and it takes them two years to master the art of predicting the synthesizer’s output and produce useful hardware. Hence the low interest in HLS 😀

      • Sandeep Sathe says:

        Hi Matthieu,

        I am Sandeep Sathe, co-founder of Sanved DA, where we developed a couple of EDA products. One is about
        SoC early stage architecture exploration and throughput estimation, and another was an FPGA IP Power

        I have also been reading and contemplating about HLS, off and on, and I use plain old verilog when it comes to writing a hardware code.

        Now Verilog code is at the details of flop and gate level. For HLS to replace verilog it has to generate
        netlist. In fact I see that as a main decision making to be implemented by HLS software. i.e to convert
        a lump of software piece into flops and combo logic, also considering target frequncy and target library
        at the minimum….

        I think this is the tool I am visualizing. For example, an AHB-based DMA Controller coded in C/C++ gets converted into netlist (or even verilog) and tool generates different netlist/flop placement for target frequency of 100MHz vs 500MHz

        Some more points might show up if I think throught it little more.


  4. Reiner says:

    Your CAPTCHA is a riddle, very difficult to solve. This is the 4th attempt.

    High level synthesis is not new. Already during the 80ies a lot has been published.
    Even a few high level synthesis workshops have been held during the 80ies.
    The third High-Level Synthesis Workshop was held in January 1988 at Orcas Island, Washington.
    High level synthesis was implemented even elready inside early hardware simulators.
    For instance
    Because of many design tools many users did not need to learn High level synthesis theory.

    • Sorry about the CAPTCHA, I have no power over it, you’ll have to take it with the EDACafe administrators.
      Thanks for your input, so it turns out that HLS is even older than I thought! I think HLS is the perfect proof that even if an idea may be awesome *on paper* (“put software in, get hardware out” or as one tool once put it, “program in chip out”, one can always dream lol), when implemented the reality is often very different.

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