Dispatches from Boston
Boston-based Nanette Collins is the 2013 recipient of the Marie R. Pistilli Women in EDA Achievement Award, presented annually to an individual who has helped advance women in the EDA industry. She started Nanette V. Collins Marketing and Public Relations in 1994 after working as director of … More »
Meet the Company that’s ProPlus Design Solutions
May 17th, 2013 by Nanette Collins
How is it that an EDA tool is old enough to celebrate its 20 birthday and still be popular and well used? The tool is advanced device modeling software and part of the unusual story of ProPlus Design Solutions.
ProPlus is a company with deep roots that go back to its founding as BTA Technology in 1993, a merger with Ultima in 2001 to what became Celestry and an acquisition by Cadence in 2003.
Come along with me as we take a circuitous journey to the company with loads of talent and loads of accomplishments that became ProPlus.
A Long and Storied History
At Berkeley, Zhihong co-developed BSIM3v3 that became the industry standard model for IC designs in 1995 and still widely adopted today. As a co-founder of BTA, he served as vice president of engineering, assuming the role of president and CEO in 1995. He led the development of the industry’s golden device modeling platform, the BSIMPro product family, employed by all the leading foundries and semiconductor companies even today.
As an EDA player growing in stature, BTA Technology merged with Ultima and formed Celestry in 2001. Celestry was noted for its UltraSim fast circuit simulator and the Nautilus full-chip verification suite with signal integrity, delay calculation, and RC extraction. DAC attendees may remember the Celestry booth crew dressed one year in white lab coats with stethoscopes around their necks.
Then came the Cadence acquisition in 2003. As the Celestry team assimilated into Cadence, it became clear that the companies’ products, visions and, perhaps, philosophies didn’t gel as well as expected. Cadence wanted a fast simulator, which it got. Celestry’s goal was to make device technology more accessible to designers, bridging the gap between device physics and design.
After a few years with Cadence, the core engineering team bought out what had been Celestry, including a majority of its products and customers, in 2006 with Cadence’s blessing to create ProPlus. Zhihong, who was corporate vice president for CSV R&D at Cadence, served as the board chairman since its founding and joined in 2010.
ProPlus now employs about 150 people, 100 of whom are part of the R&D team in China, while 30 work from its U.S. headquarters in San Jose, Calif. The others work in various regions throughout Asia. Of those 150 employees, about 30 are long-time veterans of BTA, Celestry, Cadence and now ProPlus, an unusual feat in any industry and just about unheard of in EDA.
Not all 150 employees of ProPlus will be at DAC this year in Austin, Texas, but many of them will be, ready to take attendees on a journey “From Nano-Scale Modeling to Giga-Scale Simulations.” The entire DFY product portfolio will be demonstrated in Booth #1525 and there might be a birthday cake for BSIMProPlus, the 20-year old modeling platform for nanometer devices. Over the three days of DAC, attendees will learn about:
ProPlus will celebrate BSIMProPlus’ 20th anniversary, its new products and DAC’s 50 years of innovation as a contributing sponsor of Kickin’ it Up in Austin and host a daily drawing in its booth for an iPad mini and Samsung Galaxy Tab 2.
The accomplishments continue. Zhihong led a development team that produced the 9812D noise measurement system, delivering high accuracy, 10-megahertz (MHz) measurement bandwidth and increased measurement throughput over the decades old 9812B, another ProPlus industry golden standard for 1/f noise characterization.
Savvy EDACafe readers may wonder how 9812B is obsolete while BSIMProPlus modeling platform is useable and quite widely deployed. According to Zhihong, BSIMProPlus is being constantly enhanced and improved upon.
Zhihong’s passionate about 9812D and recently hosted a webinar on the topic of noise titled, “Accurate and Efficient Wideband On-wafer Flicker (1/f) Noise Measurement,” found at: http://tiny.cc/96sxww.
ProPlus hosted two other webinars within the last six months, including, “Giga-Scale Parallel SPICE Simulator taking Pure SPICE Capacity to the 100M+ Element Level.” The other addressed “Advanced Yield Analysis and Optimization with 3-6 Sigma Statistical Simulations for Memory, Logic, Digital and Analog Designs.” Both can be found at: http://tiny.cc/ijg1ww.
The goal to bridge device manufacturing and IC design is being met by the ProPlus team and we likely can expect another 20 years of accomplishments. Don’t just take my word on ProPlus. Stop by the ProPlus Booth (#1525) to see for yourself how its developed a complete suite of DFY tools all integrated together.
P.S.: Zhihong worked with the DAC Pavilion Panel Committee to organize a pavilion panel titled, “Learn the Secrets of Design for Yield,” moderated by Pete Singer, editor in chief of Solid State Technology. It will be held Wednesday, June 5, from 1:30-2:15 p.m. on the exhibit floor in Booth #509. Panelists are: Dr. Min-Chie Jeng of TSMC, Dr. Luigi Capodieci with GLOBALFOUNDRIES, and Dr. Shaofeng Yu from SMIC.