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 Verification is No Simulation

Posts Tagged ‘OVM’

Parameterized Classes, Static Members and the Factory Macros

Monday, February 14th, 2011

Somebody asked me a simple question: Why do need two different macros (`ovm_object_utils and `ovm_object_param_utils) to register classes with the factory, and why can’t it tell me when I’ve used the wrong one? The answer turns out to be quite long, and demonstrates the dangers of using certain macros without first understanding the code behind them. Some I’m posting the response here. Adam Erickson will be presenting a paper Are Macros in OVM & UVM Evil? at the upcoming DVCon11 on Wednesday, March 2nd that goes into more details about the costs and benefits of the OVM macros.

First I need to talk about parameterized classes in SystemVerilog and how they interact with static members of those kinds of classes.

When you declare a parameterized class, it is more like a template, or generic class than a real class type. Only specializations of parameterized classes are real types. Suppose I have the two class definitions in the table below:

Un-parameterized Parameterized
class A;
static string name = “packet”;
endclass
class B #(int w=1);
static string name = “packet”;
endclass

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