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	<title>Comments for Verification is No Simulation</title>
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	<description>Just another EDA Blogs weblog</description>
	<lastBuildDate>Tue, 03 Jan 2012 23:32:24 +0000</lastBuildDate>
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		<title>Comment on Are SystemVerilog Program Blocks Needed? by Noah Kanovsky</title>
		<link>http://www10.edacafe.com/blogs/daverich/2009/06/04/hello-world/comment-page-1/#comment-172</link>
		<dc:creator>Noah Kanovsky</dc:creator>
		<pubDate>Tue, 03 Jan 2012 23:32:24 +0000</pubDate>
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		<description>I love the last comment! I have been looking into SV for the last few weeks, and before that I wrote code in SV a couple of years ago. I have the same impression of the language. The &quot;many hands&quot; I have referred to as &quot;too many cooks&quot;, and the bloat I have referred to as mish-mash. So nice to hear someone else say the same, and someone of such prominence as you!
BTW, where do you talk about virtual interfaces?</description>
		<content:encoded><![CDATA[<p>I love the last comment! I have been looking into SV for the last few weeks, and before that I wrote code in SV a couple of years ago. I have the same impression of the language. The &#8220;many hands&#8221; I have referred to as &#8220;too many cooks&#8221;, and the bloat I have referred to as mish-mash. So nice to hear someone else say the same, and someone of such prominence as you!<br />
BTW, where do you talk about virtual interfaces?</p>
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