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 Verification is No Simulation
Dave Rich
Dave Rich
Dave Rich is Verification Technologist at Mentor Graphics and is one of the authors of Mentor’s Advanced Verification Methodology cookbook. He began his career as a design and verification engineer in 1981 at Data General. In 1987, he joined Gateway Design Automation as one of the first … More »

SystemVerilog: The finer details of $root versus $unit

 
September 25th, 2009 by Dave Rich

Another installment of “Longwinded Answers to Frequent SystemVerilog Questions: $unit versus $root”

Believe me – I tried to make this shorter. It’s difficult for me to explain things without a historical perspective.

Verilog was invented to be an interpreted language. Verilog-XL was (and still is) an interpretive engine with single compilation unit use model. In an interpreted engine, all of the source code is parsed and loaded into memory. This means you have to specify all the source files of a design, including the source files of any required libraries, within a single command line before simulating.

VCS (Verilog Compiled Simulator) continued this single compilation use model even though it compiled the code into a machine object saved on disk. Later, it introduced an incremental compile feature that only compiled certain files that needed it, but you still had to specify all the source files on the command line. This is not the same as separate compilation available in most software programming languages where source code can be converted into machine code independently.

Tools such as NCsim and Modelsim introduced the concept of separate compilation, loosely based on the work library concept from VHDL. This is relatively easy to do in Verilog because module definitions are self contained. However, parameter overrides and hierarchical references limit the amount of machine code you can generate. The elaboration step does a lot of this work. It turns out that module instantiation syntax is easy to recognize, so the compiler does not need to see the definition of module that is being instantiating beforehand.

Superlog, the predecessor to SystemVerilog, was also invented as an interpreted language. It introduced the concept of $root as a global scope that allowed any kind of declaration (data types classes, variables) along with module definitions nested in that global scope. Any uninstantiated module becomes implicitly instantiated in $root. That’s fine for a single compilation unit, but you can no longer separately compile modules because they now may have dependencies on declarations outside their scope. For example

class C;
endclass
module top;
C c_h;
endmodule

There’s no problem if this is compiled as a single file, but if module top were to be compiled separately from the class C definition, it wouldn’t know what the identifier C was supposed to represent, and wouldn’t be able to parse the file.

So the IEEE committee borrowed the concept of packages from VHDL and standardized the concept of a compilation unit. A package allows you to compile definitions in a separate step and import those definitions into another compilation step. Packages create separate namespaces for those definitions as wall as imposing compilation order dependencies.

A compilation unit formalizes a scope that represents what is visible in a compilation step – called $unit in SystemVerilog. If you have a design that is compiled as a single compilation unit, there is really no conceptual difference between $unit and $root. However, once you have a design with multiple compilation units, then $unit represents the top level of each compilation unit, and there is nothing in $root except for the implicitly instantiated module instances. The only time you need to use $root or $unit is when a local name in the current scope hides a name in a higher level scope. For example

Compilation unit 1

function void print; $display("comp1"); endfunction module mod1;
  mod2 m2();

 function void print;
   $display("mod1");
 endfunction
  initial $unit::print(); // prints “comp1”
          //print() would print “mod1”)
endmodule

Compilation unit 2

function void print; $display("comp2"); endfunction module mod2;
  mod3 mod1(); // same name as top-level module
  function void print;
    $display("mod2");
  endfunction
  initial $root.mod1.print(); // print “mod1”
          // mod1.print() would print “mod3”
endmodule
module mod3;
 function void print;
   $display("mod3");
 endfunction
endmodule

This example prints “comp1” and “mod1” in either order. Note that there is no way for compilation unit 1 to directly refer to anything in compilation unit 2, or the other way around.

I hope this clears up some of the confusion between $root and $unit in SystemVerilog.

Dave Rich

http://blogs.mentor.com/nosimulation/blog/2009/09/25/unit-vs-root/

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