Brett Cline is vice president of marketing and sales at Forte Design Systems. Before joining Forte in 1999, he was Director of Marketing at Summit Design, where he managed both the verification product line, including HDL Score, and marketing communications. Cline joined Summit through the … More »
High-Level Synthesis is not just for Hardware Designers, It’s for Verification Engineers, too!
September 6th, 2012 by Brett Cline
We’ve seen an uptick in interest in high-level synthesis (HLS) around the world lately. Some of the increased interest is from designers that have MBOs to investigate HLS in 2012. Some interest is from the visibility that Forte’s Cynthesizer and HLS have had this year. And some is from people that simply do not have enough time to get their projects done with the allocated resources. This is where we can really help.
Cynthesizer automates many of the mundane coding tasks that hardware designers have to suffer with using Verilog daily. Through that automation, it will allow designers to quickly perform “what if analysis” on their macro and micro-architectural decisions without wasting months of effort.
Since the design model will now be in SystemC, a C++ class library, the functional code will be written in C or C++. Technically, it’s all C++ because we are using a C++ compiler, but the reality is that ANSI-C can pretty much be used as-is. The benefit of SystemC and C++ come from the addition of hierarchy, clock and bit accuracy, and other hardware specifics not available in standard ANSI-C. And, since SystemC is an IEEE standard, designers know that they are being locked into a proprietary language or set of extensions.
We are often asked about the verification benefits of using SystemC models for design and it’s a great question. While there are numerous others, here are three areas that will benefit from the higher-level approach.
First, hardware design and verification teams will benefit from significantly higher performance models. SystemC models typically run between 10x and 100x faster than RTL Verilog and even faster in some cases. This allows verification teams to setup and debug their verification environment faster, as well as run far more cycles through the high-level model. Since the model can be either a transaction-level model (TLM) or a pin-cycle accurate model (PCA), the verification team can vary the level of interface detail while maintaining high-level functional code.
Second, this model can be used for Virtual System Prototypes (VSPs). These highly abstracted models require far less code to implement (usually 10-20x less code) and are available months before the RTL designs.
Third, the SystemC model with HLS can be quickly targeted for an acceleration or emulation platform, including some of the big emulator “boxes” as well has home-grown FPGA solutions. This flow gives design and verification teams the best of both worlds –– the ability to quickly make changes, and get results into the hardware and get hardware accurate simulations at high speeds. Since SystemC models for Cynthesizer are technology independent, they can be quickly retargeted from FPGA to ASIC and back saving time.
Obviously, some of these benefits are hard to quantify. If we simply look at hardware verification benefits, we can quantify some. Working with a design team, we collected data using an ARM bus-based multi-function printer system. The design consisted of several blocks, both control and datapath, entirely in SystemC.
Here’s a look at simulation performance and the huge difference between the TLM behavioral model and the Verilog RTL model –– almost 500x!:
* This is a process by which the Cynthesizer RTL output is converted to cycle accurate SystemC and simulated in SystemC.
We also measured lines of code for each design:
While generated code tends to be a bit more verbose than handwritten Verilog RTL code, it’s not off by much and it’s easy to see a 10x reduction here. In a paper published at DVCon 2012, a Cynthesizer user claimed a nearly 40x reduction in code. Now that is productivity improvement!
SystemC and HLS provide a myriad of benefits to the designers in the form of better productivity, better quality of results (QoR), and true design reuse through technology-independent design. What had been less clear are the substantial benefits in verification as well.
From high-level models developed much faster to high-speed verification, high-level synthesis really is about delivering a better methodology. It allows designers and verification engineers to spend time on real hardware design problems, not on mundane tasks required by the 20+ year old Verilog RTL methodology.
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