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Archive for September 6th, 2012

High-Level Synthesis is not just for Hardware Designers, It’s for Verification Engineers, too!

Thursday, September 6th, 2012

We’ve seen an uptick in interest in high-level synthesis (HLS) around the world lately. Some of the increased interest is from designers that have MBOs to investigate HLS in 2012. Some interest is from the visibility that Forte’s Cynthesizer and HLS have had this year. And some is from people that simply do not have enough time to get their projects done with the allocated resources. This is where we can really help.

Cynthesizer automates many of the mundane coding tasks that hardware designers have to suffer with using Verilog daily. Through that automation, it will allow designers to quickly perform “what if analysis” on their macro and micro-architectural decisions without wasting months of effort.


CST: eseminar
TrueCircuits: IoTPLL

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