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Posts Tagged ‘visually-assisted automation’

Custom Compiler at DAC 2016

Monday, August 8th, 2016

DAC 2016 saw the first Synopsys custom design luncheon to feature Custom Compiler. It was a sold out event with 150 customer attendees eager to hear from Synopsys and other customers about how Synopsys is progressing in the custom design space. Antun Domic, Executive VP and General Manager of Synopsys’ Design Group moderated the event which included speakers from STMicroelectronics, GSI Technology, Samsung Foundry and the Synopsys IP team. For those of you who missed the live event, following is a short summary of the event highlights.

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Antun opened the proceedings and presented Synopsys’ fresh approach to custom layout with Custom Compiler. He shared details of the pioneering visually-assisted automation technologies that speed up custom design tasks, reduce iterations and enable reuse.

Antun then went on to introduce each of the customer speakers who related their experiences using Custom Compiler and how visually-assisted automation helped them reduce their layout efforts from days to hours.

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Custom Compiler In-Design Assistants (Part 1)

Saturday, June 18th, 2016

On-line Design Rule Checking (DRC) is nothing new. The technology has been in use for years in a variety of different layout editors and yet nearly every layout engineer has a love/hate relationship with it. Why? Well it really comes down to the use model and the responsiveness of the application.

At the beginning of the design process, layout engineers love on-line DRC. But as the design progresses, the relationship begins to sour. The problem is that as the layout gets bigger and more complex, the performance invariably starts to fall off until it reaches a point where it becomes unacceptable and the layout engineer simply turns it off and resorts to running the occasional batch checks.

To really be effective, on-line DRC has to be an interactive tool that is run often during the layout process, so, as such it needs to have a simple use model and have a fast response. The engine needs to be ‘built-in’ to deliver the required performance and the feedback needs to be comprehensive enough to enable the layout engineer to quickly fix the violation.
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Custom Compiler Layout Assistants (Part 1)

Wednesday, June 1st, 2016

As mentioned previously, on March 30th Silicon Valley was buzzing with excitement. Synopsys revealed Custom Compiler, a fresh approach to custom design that employs visually-assisted automation technologies to speed up common design tasks, reduce iterations and enable reuse at the SNUG Silicon Valley event. During this event, the R&D folks did a walkthrough of the technology ‘under-the-hood’ and showed the audience some cool layout assistants that leverage the graphical use model familiar to layout designers while eliminating the need to write complicated code and constraints. [Click here to view the videolog of the SNUG event.]

One of the layout assistants that was shown was the symbolic editor. This really is a must-have assistant when it comes to placing devices that need to be in a specific interdigitated pattern, like a differential pair. In the schematic, it is two symbols, but in the layout it could be hundreds of devices. The symbolic editor allows device placement to be edited in an easy and graphical manner and comes with a rich collection of predefined placement patterns. If you find a placement pattern you like, you can simply use it as-is and the symbolic editor will generate a correct-by-construction placement that you can instantiate in your layout. If you don’t find an exact match, you can easily use a pattern that is similar to what you need and rearrange the placement pattern graphically. No constraints to enter, no code to write and layout is done in minutes vs. hours.
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A Personal Invitation

Monday, May 23rd, 2016

I just wanted to take a moment to personally invite you to attend Synopsys’ Custom Compiler lunch event at DAC 2016 on Tuesday, June 7 in Austin, TX. At this event, engineers from GSI Technology, Samsung, STMicroelectronics, and Synopsys’ IP Group will showcase their experiences using the new Custom Compiler custom IC design tool with Visually-assisted Automation technologies.

As you’ll recall, Synopsys unveiled Custom Compiler on March 30 of this year at SNUG Silicon Valley. Custom Compiler is a new custom IC design solution that closes the FinFET productivity gap by cutting custom layout tasks from days to hours. It offers a fresh approach to custom design that employs Visually-assisted Automation technologies to speed up common design tasks, reduce iterations and enable reuse. Visually-assisted Automation technologies are a unique set of productivity aids that leverage the graphical use model familiar to layout designers while eliminating the need to write complicated code and constraints.
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Breaking News: The Wait is Over!

Wednesday, March 30th, 2016

Over the last few blogs I have outlined some of the productivity challenges that the FinFET process brings with respect to custom layout. Today Synopsys unveiled Custom Compiler and ushered in a new era of visually-assisted automation. Custom Compiler has all the good stuff I’ve been saying is needed in earlier posts: a new custom design solution that closes the FinFET productivity gap by shortening custom design tasks from days to hours.

This is not a revamp of the old constraint-based legacy approach, it’s a fresh approach to custom design that employs visually-assisted automation technologies to speed up common design tasks, reduce iterations and enable reuse.

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What’s visually-assisted automation, you may ask?

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