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What’s Really Needed for FinFET Layout (Part 2)

Tuesday, May 17th, 2016

In the last blog I outlined the kind of tool that layout engineers need in order to get a good placement that delivers robust working silicon within the confines of the FinFET process. We concluded that a guided/interactive approach that is fast and easy to refine such that you do get the result you want is the way to go.

So where else can we look for more efficiency during layout? Well, once you have placed your devices, the next step is to route up all the connections that cannot be completed by simple abutment. Again, because you could be dealing with hundreds of devices [remember the differential pair example? See the “Current Solutions for FinFET (Part 1)” blog]┬áthe routing task is one that absolutely screams out for an automatic approach, and there have been lots of efforts at automating custom routing in the past.

S2C: FPGA Base prototyping- Download white paper

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