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Posts Tagged ‘routing’

Reducing Analog Cell Layout Time with the Symbolic Editor

Thursday, December 1st, 2016

Hello again!

In the last blog post I profiled the use of Custom Compiler’s Symbolic Editor for rapid digital cell layout.

In this post, we will tackle analog cell layout and show some more of the Symbolic Editor features that enable analog layout engineers to complete their layout in minutes vs. hours.

As with the digital cell layout, engineers can take advantage of the Symbolic Editor’s ability to define multiple P and N row pairs, as shown in Figure 1.


Figure 1. Multiple Row Pairs

The preview window shows how the layout will look when realized on the layout canvas. In this example, it is clear that in order to make the design more compact, the larger transistors need to be folded.

Folding the transistors is very easy using the Symbolic Editor. Options on the toolbar allow the designer to fold the transistor by specifying either the number of segments desired or by specifying a width threshold. Once the option is set, all the layout engineer has to do is simply select the appropriate devices and have them folded such that the transistors fit neatly in the rows. Figure 2 shows how the design looks before and after folding.


Custom Compiler In-Design Assistants (Part 3)

Tuesday, September 20th, 2016

In the blog ‘Custom Compiler In-Design Assistants (Part 2)’, I outlined how we can use StarRC to report capacitances on critical nets in the layout even when the design is still in flux and not completely LVS-clean. In addition to capacitance reports, we also showed resistance reporting which is critical for FinFET-based layouts. At advanced nodes, the impact of parasitics, electromigration (EM) and restricted design rules drive critical layout choices. Interconnect that does not meet resistance, or EM criteria and unbalanced capacitances on matched nets, can and often does adversely impact layout schedules. So the earlier in the layout phase the layout engineer can address these issues, the sooner he or she can close the design.

EM in particular is a notorious problem in the FinFET process due to the high drive of the transistors and thin metals. So let’s say, for example, the layout engineer has to route a critical net which could be susceptible to the impact of EM. This is a non-trivial task that could be quite challenging. However, if you use Custom Compiler, there are some very cool capabilities that make laying out interconnect that meets EM criteria very quick and very easy.


Seeing is Believing

Sunday, August 28th, 2016

In past blogs I provided some insights into the differences between FinFET and planar CMOS designs and why layout engineers need to take these differences seriously.

In introducing Custom Compiler, Synopsys has taken a fresh approach to custom design that employs visually-assisted automation technologies to speed up common design tasks, reduce iterations, and enable reuse. But sometimes, it’s not enough to simply say that a new tool is great–engineers need to see it to believe it.

As such, Synopsys has developed a collection of short technical webisodes focusing on the unique features of Custom Compiler’s visually-assisted automation technologies that can shorten FinFET design tasks from days to hours.
The first webisode highlights how the symbolic editor enables layout engineers to create and optimize device placements at a high level of abstraction. We show how to rapidly create complex layout patterns for FinFET devices, as well as multi-row placements for PMOS and NMOS transistors, at a symbolic level without having to worry about design rules, connectivity or parameter values.
The second webisode highlights how Custom Compiler’s routing assistant enables layout engineers to route hundreds of connections with a simple click and drag of the mouse. We show how to rapidly route complex interdigitated layouts of FinFET devices, as well as simple multi-row placements for PMOS and NMOS transistors.


Custom Compiler Layout Assistants (Part 2)

Wednesday, June 15th, 2016

To all of you who attended DAC last week in Austin, TX–welcome back! I hope you were among the 175+ people who attended the Custom Compiler lunch event on Tuesday, June 7 to hear directly from engineers at GSI Technology, Samsung, STMicroelectronics and Synopsys’ IP group who described how Custom Compiler’s visually-assisted automation improves their productivity for both FinFET and established-node designs. We’ll be posting a videolog of the presentations on the Synopsys web site soon for those who missed the live event.

In the last blog I detailed the Symbolic Editor Layout Assistant and showed how the layout engineer can make simple graphical choices of how the layout needs to look and then have the placement taken care of by a placement engine. In this post I will outline another layout assistant: the Routing Assistant. The routing task is one that absolutely screams out for an automated approach, however past efforts have required a great deal of text-based constraints to get anything near to what you really want.

Custom Compiler’s Routing Assistant is a perfect combination of user guidance and automation. It’s a visually-assisted approach that allows the layout engineer to simply click on the starting point of the route and then drag the cursor in the direction they want the routing to follow. As the cursor moves along, behind the scenes the routing engine searches for connections that it can make. When it finds a connection it automatically taps to the pin without the layout engineer having to enter a mouse click. The user simply guides the router with the mouse and it fills in the routing details automatically.

What’s Really Needed for FinFET Layout (Part 2)

Tuesday, May 17th, 2016

In the last blog I outlined the kind of tool that layout engineers need in order to get a good placement that delivers robust working silicon within the confines of the FinFET process. We concluded that a guided/interactive approach that is fast and easy to refine such that you do get the result you want is the way to go.

So where else can we look for more efficiency during layout? Well, once you have placed your devices, the next step is to route up all the connections that cannot be completed by simple abutment. Again, because you could be dealing with hundreds of devices [remember the differential pair example? See the “Current Solutions for FinFET (Part 1)” blog] the routing task is one that absolutely screams out for an automatic approach, and there have been lots of efforts at automating custom routing in the past.

Hurricane FinFET (Part 3)

Friday, March 18th, 2016

Continuing on the theme of FinFET layout, let’s consider what you have to do for routing. Again drawing on the experience of my layout colleagues who are still ‘in the business’ and dealing with FinFETs, here are a few landmines you will have to deal with.

One particular issue they encounter is that although the base layers have shrunk considerably, the shrink of the routing layers has not kept pace. Each new node has brought us smaller transistors, but the minimum metal pitch has not really changed. This really impacts layout floorplanning because designs that were once dictated by device area are now dictated by the ability to route the required signals. Double-/triple-patterning compounds the issue even further.

We’ve Come a Long Way! (Part 3)

Monday, February 15th, 2016

I left off in part 2 of this blog asking the question: “Have we exhausted all avenues in our search for layout productivity?”

Although there has been no revolutionary technology as with the initial CALMA systems, there have been some incremental improvements that help oil the gears when doing layout.

On-line DRC has been one such improvement. Having the ability to check the layout for design rule violations incrementally, as you complete more and more of the design, made it easier to implement changes. Violations were displayed in the layout, making it easy to find and fix them. However, checking the layout connectivity versus the schematic was still a batch task that could only be run when the design was fully implemented. The connectivity of the physical layout had to be extracted in order to compare against the logical connectivity.

As EDA marched on, with each new crop of more powerful workstations came the next generation of interactive tools. If you could compute the design rule checks fast enough, why not show them dynamically as layout geometries were being created? And so Design-Rule-Driven (DRD) layout was born.

DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: IoTPLL

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