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Posts Tagged ‘interdigitation’

Reducing Analog Cell Layout Time with the Symbolic Editor

Thursday, December 1st, 2016

Hello again!

In the last blog post I profiled the use of Custom Compiler’s Symbolic Editor for rapid digital cell layout.

In this post, we will tackle analog cell layout and show some more of the Symbolic Editor features that enable analog layout engineers to complete their layout in minutes vs. hours.

As with the digital cell layout, engineers can take advantage of the Symbolic Editor’s ability to define multiple P and N row pairs, as shown in Figure 1.

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Figure 1. Multiple Row Pairs

The preview window shows how the layout will look when realized on the layout canvas. In this example, it is clear that in order to make the design more compact, the larger transistors need to be folded.

Folding the transistors is very easy using the Symbolic Editor. Options on the toolbar allow the designer to fold the transistor by specifying either the number of segments desired or by specifying a width threshold. Once the option is set, all the layout engineer has to do is simply select the appropriate devices and have them folded such that the transistors fit neatly in the rows. Figure 2 shows how the design looks before and after folding.

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Rapid Custom Digital Cell Layout with the Symbolic Editor

Thursday, November 3rd, 2016

In the ‘Custom Compiler Layout Assistants (Part 1)’ blog post, I profiled the use of the symbolic editor and how it makes placing devices that need to be in a specific interdigitated pattern (for example, a differential pair) very easy. With no constraints to enter and no code to write, layout is done in minutes vs. hours.

However, there is a lot more to the symbolic editor than the ability to simplify interdigitation. One good example is the ability to define multiple P and N row pairs and then symbolically chain and fold the transistors such that you get them to fit neatly in the rows. This is a key feature that allows you to not only control the aspect ratio of the design, but to very rapidly create a custom digital cell layout, as shown in Figure 1.

SED_Multi_2_croppped

Figure 1. Multiple Row Pairs

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